dds.tan.summary

基于DDS的数字移相正弦信号发生器设计

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 14.800 ns
From           : K[2]
To             : SUM99:U0|TEMP[7]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.800 ns
From           : REG2:U3|Q[0]
To             : Q[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.600 ns
From           : K[4]
To             : SUM99:U0|TEMP[4]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 76.34 MHz ( period = 13.100 ns )
From           : REG1:U1|Q[7]
To             : ROM:U2|OUTP[4]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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