ram.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram is
port(addr:in std_logic_vector(4 downto 0);--------地址选择信号
     wr:in std_logic;-----------------------------写信号
     rd:in std_logic;-----------------------------读信号
     cs:in std_logic;-----------------------------片选信号
     datain:in std_logic_vector(7 downto 0);------数据输入端
     dataout:out std_logic_vector(7 downto 0));---数据输出端
end;
architecture one of ram is
	type memory is array(0 to 31)of std_logic_vector(7 downto 0);-------定义数据类型
	signal data1:memory;
	signal addr1:integer range 0 to 31;
begin
	addr1<=conv_integer(addr);-----二进制到十进制的转换
process(wr,cs,addr1,data1,datain)------------------------写操作
begin
   if cs='0' and wr='1' then 
      data1(addr1)<=datain;
    end if;
end process;
process(rd,cs,addr1,data1)---------读操作
begin
if cs='0' and rd='1' then
     dataout<=data1(addr1);
else
     dataout<=(others=>'Z');
end if;
end process;
end;