div248.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div248 is
port(clk:in std_logic;------时钟
     div2:out std_logic;-----输出2分频信号
     div4:out std_logic;-----输出4分频信号
     div8:out std_logic);----输出8分频信号
end;
architecture one of div248 is
	signal cnt :std_logic_vector(2 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then----计数器计数
	cnt<=cnt+1;
end if;
end process;
div2<=cnt(0);
div4<=cnt(1);
div8<=cnt(2);
end;