div_half.tan.rpt

大量VHDL写的数字系统设计有用实例达到

    Info: Detected gated clock "clk_temp1" as buffer
    Info: Detected ripple clock "div~reg0" as buffer
Info: Clock "clk" has Internal fmax of 156.76 MHz between source register "count[1]" and destination register "count[29]" (period= 6.379 ns)
    Info: + Longest register to register delay is 6.115 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y18_N19; Fanout = 3; REG Node = 'count[1]'
        Info: 2: + IC(0.755 ns) + CELL(0.596 ns) = 1.351 ns; Loc. = LCCOMB_X14_Y18_N2; Fanout = 2; COMB Node = 'Add0~419'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.437 ns; Loc. = LCCOMB_X14_Y18_N4; Fanout = 2; COMB Node = 'Add0~421'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.523 ns; Loc. = LCCOMB_X14_Y18_N6; Fanout = 2; COMB Node = 'Add0~423'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.609 ns; Loc. = LCCOMB_X14_Y18_N8; Fanout = 2; COMB Node = 'Add0~425'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.695 ns; Loc. = LCCOMB_X14_Y18_N10; Fanout = 2; COMB Node = 'Add0~427'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.781 ns; Loc. = LCCOMB_X14_Y18_N12; Fanout = 2; COMB Node = 'Add0~429'
        Info: 8: + IC(0.000 ns) + CELL(0.190 ns) = 1.971 ns; Loc. = LCCOMB_X14_Y18_N14; Fanout = 2; COMB Node = 'Add0~431'
        Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.057 ns; Loc. = LCCOMB_X14_Y18_N16; Fanout = 2; COMB Node = 'Add0~433'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.143 ns; Loc. = LCCOMB_X14_Y18_N18; Fanout = 2; COMB Node = 'Add0~435'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.229 ns; Loc. = LCCOMB_X14_Y18_N20; Fanout = 2; COMB Node = 'Add0~437'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.315 ns; Loc. = LCCOMB_X14_Y18_N22; Fanout = 2; COMB Node = 'Add0~439'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.401 ns; Loc. = LCCOMB_X14_Y18_N24; Fanout = 2; COMB Node = 'Add0~441'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.487 ns; Loc. = LCCOMB_X14_Y18_N26; Fanout = 2; COMB Node = 'Add0~443'
        Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.573 ns; Loc. = LCCOMB_X14_Y18_N28; Fanout = 2; COMB Node = 'Add0~445'
        Info: 16: + IC(0.000 ns) + CELL(0.175 ns) = 2.748 ns; Loc. = LCCOMB_X14_Y18_N30; Fanout = 2; COMB Node = 'Add0~447'
        Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.834 ns; Loc. = LCCOMB_X14_Y17_N0; Fanout = 2; COMB Node = 'Add0~449'
        Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.920 ns; Loc. = LCCOMB_X14_Y17_N2; Fanout = 2; COMB Node = 'Add0~451'
        Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.006 ns; Loc. = LCCOMB_X14_Y17_N4; Fanout = 2; COMB Node = 'Add0~453'
        Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.092 ns; Loc. = LCCOMB_X14_Y17_N6; Fanout = 2; COMB Node = 'Add0~455'
        Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.178 ns; Loc. = LCCOMB_X14_Y17_N8; Fanout = 2; COMB Node = 'Add0~457'
        Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.264 ns; Loc. = LCCOMB_X14_Y17_N10; Fanout = 2; COMB Node = 'Add0~459'
        Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.350 ns; Loc. = LCCOMB_X14_Y17_N12; Fanout = 2; COMB Node = 'Add0~461'
        Info: 24: + IC(0.000 ns) + CELL(0.190 ns) = 3.540 ns; Loc. = LCCOMB_X14_Y17_N14; Fanout = 2; COMB Node = 'Add0~463'
        Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.626 ns; Loc. = LCCOMB_X14_Y17_N16; Fanout = 2; COMB Node = 'Add0~465'
        Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.712 ns; Loc. = LCCOMB_X14_Y17_N18; Fanout = 2; COMB Node = 'Add0~467'
        Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.798 ns; Loc. = LCCOMB_X14_Y17_N20; Fanout = 2; COMB Node = 'Add0~469'
        Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.884 ns; Loc. = LCCOMB_X14_Y17_N22; Fanout = 2; COMB Node = 'Add0~471'
        Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.970 ns; Loc. = LCCOMB_X14_Y17_N24; Fanout = 2; COMB Node = 'Add0~473'
        Info: 30: + IC(0.000 ns) + CELL(0.506 ns) = 4.476 ns; Loc. = LCCOMB_X14_Y17_N26; Fanout = 1; COMB Node = 'Add0~474'
        Info: 31: + IC(1.325 ns) + CELL(0.206 ns) = 6.007 ns; Loc. = LCCOMB_X13_Y18_N28; Fanout = 1; COMB Node = 'count~436'
        Info: 32: + IC(0.000 ns) + CELL(0.108 ns) = 6.115 ns; Loc. = LCFF_X13_Y18_N29; Fanout = 3; REG Node = 'count[29]'
        Info: Total cell delay = 4.035 ns ( 65.99 % )
        Info: Total interconnect delay = 2.080 ns ( 34.01 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.438 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(1.934 ns) + CELL(0.206 ns) = 3.085 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'clk_temp1'
            Info: 3: + IC(1.751 ns) + CELL(0.000 ns) = 4.836 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk_temp1~clkctrl'
            Info: 4: + IC(0.936 ns) + CELL(0.666 ns) = 6.438 ns; Loc. = LCFF_X13_Y18_N29; Fanout = 3; REG Node = 'count[29]'
            Info: Total cell delay = 1.817 ns ( 28.22 % )
            Info: Total interconnect delay = 4.621 ns ( 71.78 % )
        Info: - Longest clock path from clock "clk" to source register is 6.438 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(1.934 ns) + CELL(0.206 ns) = 3.085 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'clk_temp1'
            Info: 3: + IC(1.751 ns) + CELL(0.000 ns) = 4.836 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk_temp1~clkctrl'
            Info: 4: + IC(0.936 ns) + CELL(0.666 ns) = 6.438 ns; Loc. = LCFF_X13_Y18_N19; Fanout = 3; REG Node = 'count[1]'
            Info: Total cell delay = 1.817 ns ( 28.22 % )
            Info: Total interconnect delay = 4.621 ns ( 71.78 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "div" through register "div~reg0" is 10.875 ns
    Info: + Longest clock path from clock "clk" to source register is 6.440 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.934 ns) + CELL(0.206 ns) = 3.085 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'clk_temp1'
        Info: 3: + IC(1.751 ns) + CELL(0.000 ns) = 4.836 ns; Loc. = CLKCTRL_G4; Fanout = 33; COMB Node = 'clk_temp1~clkctrl'
        Info: 4: + IC(0.938 ns) + CELL(0.666 ns) = 6.440 ns; Loc. = LCFF_X15_Y18_N3; Fanout = 2; REG Node = 'div~reg0'
        Info: Total cell delay = 1.817 ns ( 28.21 % )
        Info: Total interconnect delay = 4.623 ns ( 71.79 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.131 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y18_N3; Fanout = 2; REG Node = 'div~reg0'
        Info: 2: + IC(0.915 ns) + CELL(3.216 ns) = 4.131 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'div'
        Info: Total cell delay = 3.216 ns ( 77.85 % )
        Info: Total interconnect delay = 0.915 ns ( 22.15 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Sat Mar 31 21:23:01 2007
    Info: Elapsed time: 00:00:01