siso4_1.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity siso4_1 is
port(clk:in std_logic;----时钟
     din:in std_logic;----数据输入端
     dout:out std_logic);----数据输出端
end;
architecture one of siso4_1 is
	signal q:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then---移位
   q(0)<=din;
   q(3 downto 1)<=q(2 downto 0);
end if;
end process;
dout<=q(3);
end;