cnt4_top_1.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt4:inst1\|q1\[0\] cnt4:inst1\|q1\[2\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"cnt4:inst1\|q1\[0\]\" and destination register \"cnt4:inst1\|q1\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.491 ns + Longest register register " "Info: + Longest register to register delay is 1.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt4:inst1\|q1\[0\] 1 REG LCFF_X1_Y8_N19 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1\|q1\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4:inst1|q1[0] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.759 ns) + CELL(0.624 ns) 1.383 ns cnt4:inst1\|q1\[2\]~150 2 COMB LCCOMB_X1_Y8_N22 1 " "Info: 2: + IC(0.759 ns) + CELL(0.624 ns) = 1.383 ns; Loc. = LCCOMB_X1_Y8_N22; Fanout = 1; COMB Node = 'cnt4:inst1\|q1\[2\]~150'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.383 ns" { cnt4:inst1|q1[0] cnt4:inst1|q1[2]~150 } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.491 ns cnt4:inst1\|q1\[2\] 3 REG LCFF_X1_Y8_N23 9 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.491 ns; Loc. = LCFF_X1_Y8_N23; Fanout = 9; REG Node = 'cnt4:inst1\|q1\[2\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { cnt4:inst1|q1[2]~150 cnt4:inst1|q1[2] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.732 ns ( 49.09 % ) " "Info: Total cell delay = 0.732 ns ( 49.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.759 ns ( 50.91 % ) " "Info: Total interconnect delay = 0.759 ns ( 50.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { cnt4:inst1|q1[0] cnt4:inst1|q1[2]~150 cnt4:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.491 ns" { cnt4:inst1|q1[0] cnt4:inst1|q1[2]~150 cnt4:inst1|q1[2] } { 0.000ns 0.759ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.785 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns cnt4:inst1\|q1\[2\] 3 REG LCFF_X1_Y8_N23 9 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N23; Fanout = 9; REG Node = 'cnt4:inst1\|q1\[2\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk~clkctrl cnt4:inst1|q1[2] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[2] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.785 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns cnt4:inst1\|q1\[0\] 3 REG LCFF_X1_Y8_N19 11 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1\|q1\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[2] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { cnt4:inst1|q1[0] cnt4:inst1|q1[2]~150 cnt4:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.491 ns" { cnt4:inst1|q1[0] cnt4:inst1|q1[2]~150 cnt4:inst1|q1[2] } { 0.000ns 0.759ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[2] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { cnt4:inst1|q1[2] } {  } {  } "" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "cnt4:inst1\|q1\[3\] en clk 0.595 ns register " "Info: tsu for register \"cnt4:inst1\|q1\[3\]\" (data pin = \"en\", clock pin = \"clk\") is 0.595 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.420 ns + Longest pin register " "Info: + Longest pin to register delay is 3.420 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns en 1 PIN PIN_18 5 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 5; PIN Node = 'en'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 120 -64 104 136 "en" "" } { 112 104 152 128 "en" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.589 ns) 2.708 ns cnt4:inst1\|q1\[1\]~151 2 COMB LCCOMB_X1_Y8_N10 1 " "Info: 2: + IC(1.029 ns) + CELL(0.589 ns) = 2.708 ns; Loc. = LCCOMB_X1_Y8_N10; Fanout = 1; COMB Node = 'cnt4:inst1\|q1\[1\]~151'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.618 ns" { en cnt4:inst1|q1[1]~151 } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.206 ns) 3.312 ns cnt4:inst1\|q1\[3\]~152 3 COMB LCCOMB_X1_Y8_N26 1 " "Info: 3: + IC(0.398 ns) + CELL(0.206 ns) = 3.312 ns; Loc. = LCCOMB_X1_Y8_N26; Fanout = 1; COMB Node = 'cnt4:inst1\|q1\[3\]~152'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.604 ns" { cnt4:inst1|q1[1]~151 cnt4:inst1|q1[3]~152 } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.420 ns cnt4:inst1\|q1\[3\] 4 REG LCFF_X1_Y8_N27 8 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.420 ns; Loc. = LCFF_X1_Y8_N27; Fanout = 8; REG Node = 'cnt4:inst1\|q1\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { cnt4:inst1|q1[3]~152 cnt4:inst1|q1[3] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.993 ns ( 58.27 % ) " "Info: Total cell delay = 1.993 ns ( 58.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.427 ns ( 41.73 % ) " "Info: Total interconnect delay = 1.427 ns ( 41.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.420 ns" { en cnt4:inst1|q1[1]~151 cnt4:inst1|q1[3]~152 cnt4:inst1|q1[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.420 ns" { en en~combout cnt4:inst1|q1[1]~151 cnt4:inst1|q1[3]~152 cnt4:inst1|q1[3] } { 0.000ns 0.000ns 1.029ns 0.398ns 0.000ns } { 0.000ns 1.090ns 0.589ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.785 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns cnt4:inst1\|q1\[3\] 3 REG LCFF_X1_Y8_N27 8 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N27; Fanout = 8; REG Node = 'cnt4:inst1\|q1\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk~clkctrl cnt4:inst1|q1[3] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[3] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.420 ns" { en cnt4:inst1|q1[1]~151 cnt4:inst1|q1[3]~152 cnt4:inst1|q1[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.420 ns" { en en~combout cnt4:inst1|q1[1]~151 cnt4:inst1|q1[3]~152 cnt4:inst1|q1[3] } { 0.000ns 0.000ns 1.029ns 0.398ns 0.000ns } { 0.000ns 1.090ns 0.589ns 0.206ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[3] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[5\] cnt4:inst1\|q1\[0\] 8.993 ns register " "Info: tco from clock \"clk\" to destination pin \"y\[5\]\" through register \"cnt4:inst1\|q1\[0\]\" is 8.993 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.785 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns cnt4:inst1\|q1\[0\] 3 REG LCFF_X1_Y8_N19 11 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1\|q1\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.904 ns + Longest register pin " "Info: + Longest register to pin delay is 5.904 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt4:inst1\|q1\[0\] 1 REG LCFF_X1_Y8_N19 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1\|q1\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4:inst1|q1[0] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.370 ns) 1.184 ns bcd_decoder:inst2\|Mux2~29 2 COMB LCCOMB_X1_Y8_N4 1 " "Info: 2: + IC(0.814 ns) + CELL(0.370 ns) = 1.184 ns; Loc. = LCCOMB_X1_Y8_N4; Fanout = 1; COMB Node = 'bcd_decoder:inst2\|Mux2~29'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.184 ns" { cnt4:inst1|q1[0] bcd_decoder:inst2|Mux2~29 } "NODE_NAME" } } { "bcd_decoder.vhd" "" { Text "D:/my_eda/cnt4_dec_1/bcd_decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.490 ns) + CELL(3.230 ns) 5.904 ns y\[5\] 3 PIN PIN_31 0 " "Info: 3: + IC(1.490 ns) + CELL(3.230 ns) = 5.904 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'y\[5\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.720 ns" { bcd_decoder:inst2|Mux2~29 y[5] } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 120 560 736 136 "y\[7..0\]" "" } { 104 528 560 128 "y\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 60.98 % ) " "Info: Total cell delay = 3.600 ns ( 60.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.304 ns ( 39.02 % ) " "Info: Total interconnect delay = 2.304 ns ( 39.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.904 ns" { cnt4:inst1|q1[0] bcd_decoder:inst2|Mux2~29 y[5] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.904 ns" { cnt4:inst1|q1[0] bcd_decoder:inst2|Mux2~29 y[5] } { 0.000ns 0.814ns 1.490ns } { 0.000ns 0.370ns 3.230ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.904 ns" { cnt4:inst1|q1[0] bcd_decoder:inst2|Mux2~29 y[5] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.904 ns" { cnt4:inst1|q1[0] bcd_decoder:inst2|Mux2~29 y[5] } { 0.000ns 0.814ns 1.490ns } { 0.000ns 0.370ns 3.230ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "cnt4:inst1\|q1\[0\] en clk 0.664 ns register " "Info: th for register \"cnt4:inst1\|q1\[0\]\" (data pin = \"en\", clock pin = \"clk\") is 0.664 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.785 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 88 -64 104 104 "clk" "" } { 80 104 152 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns cnt4:inst1\|q1\[0\] 3 REG LCFF_X1_Y8_N19 11 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1\|q1\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.427 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns en 1 PIN PIN_18 5 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 5; PIN Node = 'en'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "cnt4_top_1.bdf" "" { Schematic "D:/my_eda/cnt4_dec_1/cnt4_top_1.bdf" { { 120 -64 104 136 "en" "" } { 112 104 152 128 "en" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.206 ns) 2.319 ns cnt4:inst1\|q1\[0\]~148 2 COMB LCCOMB_X1_Y8_N18 1 " "Info: 2: + IC(1.023 ns) + CELL(0.206 ns) = 2.319 ns; Loc. = LCCOMB_X1_Y8_N18; Fanout = 1; COMB Node = 'cnt4:inst1\|q1\[0\]~148'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.229 ns" { en cnt4:inst1|q1[0]~148 } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.427 ns cnt4:inst1\|q1\[0\] 3 REG LCFF_X1_Y8_N19 11 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.427 ns; Loc. = LCFF_X1_Y8_N19; Fanout = 11; REG Node = 'cnt4:inst1\|q1\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { cnt4:inst1|q1[0]~148 cnt4:inst1|q1[0] } "NODE_NAME" } } { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec_1/cnt4.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.404 ns ( 57.85 % ) " "Info: Total cell delay = 1.404 ns ( 57.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.023 ns ( 42.15 % ) " "Info: Total interconnect delay = 1.023 ns ( 42.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.427 ns" { en cnt4:inst1|q1[0]~148 cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.427 ns" { en en~combout cnt4:inst1|q1[0]~148 cnt4:inst1|q1[0] } { 0.000ns 0.000ns 1.023ns 0.000ns } { 0.000ns 1.090ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { clk clk~clkctrl cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { clk clk~combout clk~clkctrl cnt4:inst1|q1[0] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.427 ns" { en cnt4:inst1|q1[0]~148 cnt4:inst1|q1[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.427 ns" { en en~combout cnt4:inst1|q1[0]~148 cnt4:inst1|q1[0] } { 0.000ns 0.000ns 1.023ns 0.000ns } { 0.000ns 1.090ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}