scan_led.vho

大量VHDL写的数字系统设计有用实例达到

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

-- DATE "04/07/2007 11:05:31"

-- 
-- Device: Altera EP2C8T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	scan_led IS
    PORT (
	clk : IN std_logic;
	seg : OUT std_logic_vector(7 DOWNTO 0);
	scan : OUT std_logic_vector(7 DOWNTO 0)
	);
END scan_led;

ARCHITECTURE structure OF scan_led IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_seg : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_scan : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~combout\ : std_logic;
SIGNAL \clk~clkctrl\ : std_logic;
SIGNAL \cnt8[0]~66\ : std_logic;
SIGNAL \cnt8[1]~64\ : std_logic;
SIGNAL \Mux7~90\ : std_logic;
SIGNAL \cnt8[2]~65\ : std_logic;
SIGNAL \Mux17~34\ : std_logic;
SIGNAL \Mux16~56\ : std_logic;
SIGNAL \Mux15~29\ : std_logic;
SIGNAL \Mux14~52\ : std_logic;
SIGNAL \Mux7~91\ : std_logic;
SIGNAL \Mux12~47\ : std_logic;
SIGNAL \Mux7~92\ : std_logic;
SIGNAL \Mux7~93\ : std_logic;
SIGNAL \Mux7~94\ : std_logic;
SIGNAL \Mux7~95\ : std_logic;
SIGNAL \Mux7~96\ : std_logic;
SIGNAL \Mux7~97\ : std_logic;
SIGNAL \Mux7~98\ : std_logic;
SIGNAL \Mux7~99\ : std_logic;
SIGNAL cnt8 : std_logic_vector(2 DOWNTO 0);
SIGNAL \ALT_INV_Mux7~90\ : std_logic;
SIGNAL \ALT_INV_Mux16~56\ : std_logic;
SIGNAL \ALT_INV_Mux15~29\ : std_logic;
SIGNAL \ALT_INV_Mux14~52\ : std_logic;
SIGNAL \ALT_INV_Mux7~91\ : std_logic;
SIGNAL \ALT_INV_Mux12~47\ : std_logic;

BEGIN

ww_clk <= clk;
seg <= ww_seg;
scan <= ww_scan;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);
\ALT_INV_Mux7~90\ <= NOT \Mux7~90\;
\ALT_INV_Mux16~56\ <= NOT \Mux16~56\;
\ALT_INV_Mux15~29\ <= NOT \Mux15~29\;
\ALT_INV_Mux14~52\ <= NOT \Mux14~52\;
\ALT_INV_Mux7~91\ <= NOT \Mux7~91\;
\ALT_INV_Mux12~47\ <= NOT \Mux12~47\;

\clk~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\clk~clkctrl_I\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \clk~clkctrl_I_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~clkctrl\);

\cnt8[0]~66_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt8[0]~66\ = !cnt8(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => cnt8(0),
	combout => \cnt8[0]~66\);

\cnt8[0]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \cnt8[0]~66\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt8(0));

\cnt8[1]~64_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt8[1]~64\ = cnt8(1) $ cnt8(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => cnt8(1),
	datad => cnt8(0),
	combout => \cnt8[1]~64\);

\cnt8[1]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \cnt8[1]~64\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt8(1));

\Mux7~90_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~90\ = !cnt8(0) & !cnt8(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(0),
	datad => cnt8(1),
	combout => \Mux7~90\);

\cnt8[2]~65_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt8[2]~65\ = cnt8(2) $ (cnt8(0) & cnt8(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(0),
	datac => cnt8(2),
	datad => cnt8(1),
	combout => \cnt8[2]~65\);

\cnt8[2]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \cnt8[2]~65\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt8(2));

\Mux17~34_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux17~34\ = cnt8(2) & (cnt8(0)) # !cnt8(2) & cnt8(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux17~34\);

\Mux16~56_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux16~56\ = cnt8(1) & (!cnt8(2)) # !cnt8(1) & (cnt8(2) # !cnt8(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux16~56\);

\Mux15~29_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux15~29\ = cnt8(0) $ (!cnt8(2) # !cnt8(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux15~29\);

\Mux14~52_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux14~52\ = cnt8(0) & (cnt8(1) $ !cnt8(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux14~52\);

\Mux7~91_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~91\ = cnt8(0) & cnt8(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(0),
	datad => cnt8(1),
	combout => \Mux7~91\);

\Mux12~47_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux12~47\ = !cnt8(0) & (cnt8(1) # !cnt8(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux12~47\);

\Mux7~92_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~92\ = !cnt8(1) & !cnt8(0) & !cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~92\);

\Mux7~93_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~93\ = !cnt8(1) & cnt8(0) & !cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~93\);

\Mux7~94_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~94\ = cnt8(1) & !cnt8(0) & !cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~94\);

\Mux7~95_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~95\ = cnt8(1) & cnt8(0) & !cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~95\);

\Mux7~96_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~96\ = !cnt8(1) & !cnt8(0) & cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~96\);

\Mux7~97_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~97\ = !cnt8(1) & cnt8(0) & cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~97\);

\Mux7~98_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~98\ = cnt8(1) & !cnt8(0) & cnt8(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt8(1),
	datac => cnt8(0),
	datad => cnt8(2),
	combout => \Mux7~98\);

\Mux7~99_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Mux7~99\ = cnt8(1) & cnt8(0) & cnt8(2)

-- pragma translate_off