shop.tan.summary

大量VHDL写的数字系统设计有用实例达到

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.929 ns
From           : set
To             : ram[2][6]~1933
From Clock     : --
To Clock       : set
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.614 ns
From           : coin[0]
To             : seg7[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.726 ns
From           : get
To             : act10~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 126.14 MHz ( period = 7.928 ns )
From           : item[1]
To             : qua[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'set'
Slack          : N/A
Required Time  : None
Actual Time    : 172.50 MHz ( period = 5.797 ns )
From           : ram[1][7]~1977
To             : ram[1][7]~1977
From Clock     : set
To Clock       : set
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------