lpm_fifo.fit.summary

来自「大量VHDL写的数字系统设计有用实例达到」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Mon Apr 23 16:20:10 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : lpm_fifo
Top-level Entity Name : lpm_fifo
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 34 / 10,570 ( < 1 % )
Total pins : 26 / 336 ( 8 % )
Total virtual pins : 0
Total memory bits : 256 / 920,448 ( < 1 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )