led.vho

来自「大量VHDL写的数字系统设计有用实例达到」· VHO 代码 · 共 1,170 行 · 第 1/2 页
VHO
1,170 行
	clk => \clk~clkctrl\,
	datain => \Selector4~61\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(3));

\Equal0~108_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Equal0~108\ = !q1(0) & !q1(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => q1(0),
	datad => q1(1),
	combout => \Equal0~108\);

\Selector1~137_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector1~137\ = !\present.s1\ & !\present.s3\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \present.s1\,
	datac => \present.s3\,
	combout => \Selector1~137\);

\q1~435_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1~435\ = q1(5) & (!count(1) # !count(0) # !count(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(2),
	datab => q1(5),
	datac => count(0),
	datad => count(1),
	combout => \q1~435\);

\q1~436_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1~436\ = q1(7) & (!count(1) # !count(2) # !count(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => q1(7),
	datab => count(0),
	datac => count(2),
	datad => count(1),
	combout => \q1~436\);

\Selector3~59_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector3~59\ = \q1[3]~434\ & (\q1~436\ & \q1[3]~433\) # !\q1[3]~434\ & (q1(5) # !\q1[3]~433\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => q1(5),
	datab => \q1~436\,
	datac => \q1[3]~434\,
	datad => \q1[3]~433\,
	combout => \Selector3~59\);

\Selector3~60_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector3~60\ = \q1[3]~431\ & (\Selector3~59\ & (\q1~435\) # !\Selector3~59\ & \q1~427\) # !\q1[3]~431\ & (\Selector3~59\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \q1~427\,
	datab => \q1[3]~431\,
	datac => \q1~435\,
	datad => \Selector3~59\,
	combout => \Selector3~60\);

\Selector3~61_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector3~61\ = \Selector3~60\ & (\present.s1\ # !\q1[3]~431\ # !\Equal0~110\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s1\,
	datab => \Equal0~110\,
	datac => \q1[3]~431\,
	datad => \Selector3~60\,
	combout => \Selector3~61\);

\q1[4]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector3~61\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(4));

\q1~429_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1~429\ = q1(4) & (!count(2) # !count(1) # !count(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(0),
	datab => q1(4),
	datac => count(1),
	datad => count(2),
	combout => \q1~429\);

\Selector1~138_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector1~138\ = \Selector2~147\ & (\q1~436\ # \q1~435\ & !\Selector1~137\) # !\Selector2~147\ & \q1~435\ & (!\Selector1~137\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000011101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Selector2~147\,
	datab => \q1~435\,
	datac => \q1~436\,
	datad => \Selector1~137\,
	combout => \Selector1~138\);

\q1[6]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector1~138\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(6));

\Selector2~146_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector2~146\ = q1(6) & (!count(0) # !count(1) # !count(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(2),
	datab => q1(6),
	datac => count(1),
	datad => count(0),
	combout => \Selector2~146\);

\Selector2~148_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector2~148\ = \Selector2~147\ & (\Selector2~146\ # !\Selector1~137\ & \q1~429\) # !\Selector2~147\ & !\Selector1~137\ & \q1~429\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Selector2~147\,
	datab => \Selector1~137\,
	datac => \q1~429\,
	datad => \Selector2~146\,
	combout => \Selector2~148\);

\q1[5]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector2~148\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(5));

\Selector0~173_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector0~173\ = q1(6) # count(0) & count(2) & count(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(0),
	datab => count(2),
	datac => q1(6),
	datad => count(1),
	combout => \Selector0~173\);

\Selector0~174_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector0~174\ = \q1~429\ & (\present.s2\ # \Selector0~173\ & !\Selector1~137\) # !\q1~429\ & (\Selector0~173\ & !\Selector1~137\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100011111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \q1~429\,
	datab => \present.s2\,
	datac => \Selector0~173\,
	datad => \Selector1~137\,
	combout => \Selector0~174\);

\Selector0~175_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector0~175\ = \Selector0~174\ # !\present.s0\ & (\Equal0~110\ # \q1~432\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100110010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Equal0~110\,
	datab => \present.s0\,
	datac => \q1~432\,
	datad => \Selector0~174\,
	combout => \Selector0~175\);

\q1[7]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector0~175\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(7));

\Equal0~109_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Equal0~109\ = !q1(4) & !q1(5) & !q1(7) & !q1(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => q1(4),
	datab => q1(5),
	datac => q1(7),
	datad => q1(6),
	combout => \Equal0~109\);

\Equal0~110_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Equal0~110\ = !q1(2) & !q1(3) & \Equal0~108\ & \Equal0~109\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => q1(2),
	datab => q1(3),
	datac => \Equal0~108\,
	datad => \Equal0~109\,
	combout => \Equal0~110\);

\q1~427_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1~427\ = q1(3) & (!count(1) # !count(2) # !count(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(0),
	datab => q1(3),
	datac => count(2),
	datad => count(1),
	combout => \q1~427\);

\Selector7~312_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector7~312\ = \present.s3\ & !\Equal1~44\ & q1(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s3\,
	datac => \Equal1~44\,
	datad => q1(1),
	combout => \Selector7~312\);

\Selector7~313_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector7~313\ = \present.s1\ & (\Equal1~44\ # q1(7))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \present.s1\,
	datac => \Equal1~44\,
	datad => q1(7),
	combout => \Selector7~313\);

\Selector7~314_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector7~314\ = \Selector7~312\ # \Selector7~313\ # \present.s2\ & \q1~427\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s2\,
	datab => \q1~427\,
	datac => \Selector7~312\,
	datad => \Selector7~313\,
	combout => \Selector7~314\);

\Selector7~316_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector7~316\ = \Selector7~314\ # \Selector7~315\ & !\Equal0~110\ & !\present.s0\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Selector7~315\,
	datab => \Equal0~110\,
	datac => \present.s0\,
	datad => \Selector7~314\,
	combout => \Selector7~316\);

\q1[0]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector7~316\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(0));

\q[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(0));

\q[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(1));

\q[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(2));

\q[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(3));

\q[4]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(4),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(4));

\q[5]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(5),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(5));

\q[6]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(6),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(6));

\q[7]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => q1(7),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_q(7));
END structure;
led.vho - 源码说明

本页面展示了「大量VHDL写的数字系统设计有用实例达到」中的 led.vho 源码文件，采用 VHO 编程语言编写，共 1,170 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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