led.vho

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VHO
1,170 行
字号
12
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

-- DATE "04/06/2007 16:25:37"

-- 
-- Device: Altera EP2C8T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	led IS
    PORT (
	clk : IN std_logic;
	rst : IN std_logic;
	q : OUT std_logic_vector(7 DOWNTO 0)
	);
END led;

ARCHITECTURE structure OF led IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_q : std_logic_vector(7 DOWNTO 0);
SIGNAL \rst~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Selector7~315\ : std_logic;
SIGNAL \Selector2~147\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \clk~clkctrl\ : std_logic;
SIGNAL \count[0]~207\ : std_logic;
SIGNAL \rst~combout\ : std_logic;
SIGNAL \count[0]~204\ : std_logic;
SIGNAL \count[1]~206\ : std_logic;
SIGNAL \count[2]~205\ : std_logic;
SIGNAL \Equal1~44\ : std_logic;
SIGNAL \Selector13~118\ : std_logic;
SIGNAL \rst~clkctrl\ : std_logic;
SIGNAL \present.s1\ : std_logic;
SIGNAL \present.s2\ : std_logic;
SIGNAL \present.s3\ : std_logic;
SIGNAL \q1[3]~431\ : std_logic;
SIGNAL \Selector12~126\ : std_logic;
SIGNAL \present.s0\ : std_logic;
SIGNAL \q1[1]~428\ : std_logic;
SIGNAL \Selector6~133\ : std_logic;
SIGNAL \Selector5~133\ : std_logic;
SIGNAL \q1~430\ : std_logic;
SIGNAL \q1~432\ : std_logic;
SIGNAL \q1[3]~434\ : std_logic;
SIGNAL \q1[3]~433\ : std_logic;
SIGNAL \Selector4~59\ : std_logic;
SIGNAL \Selector4~60\ : std_logic;
SIGNAL \Selector4~61\ : std_logic;
SIGNAL \Equal0~108\ : std_logic;
SIGNAL \Selector1~137\ : std_logic;
SIGNAL \q1~435\ : std_logic;
SIGNAL \q1~436\ : std_logic;
SIGNAL \Selector3~59\ : std_logic;
SIGNAL \Selector3~60\ : std_logic;
SIGNAL \Selector3~61\ : std_logic;
SIGNAL \q1~429\ : std_logic;
SIGNAL \Selector1~138\ : std_logic;
SIGNAL \Selector2~146\ : std_logic;
SIGNAL \Selector2~148\ : std_logic;
SIGNAL \Selector0~173\ : std_logic;
SIGNAL \Selector0~174\ : std_logic;
SIGNAL \Selector0~175\ : std_logic;
SIGNAL \Equal0~109\ : std_logic;
SIGNAL \Equal0~110\ : std_logic;
SIGNAL \q1~427\ : std_logic;
SIGNAL \Selector7~312\ : std_logic;
SIGNAL \Selector7~313\ : std_logic;
SIGNAL \Selector7~314\ : std_logic;
SIGNAL \Selector7~316\ : std_logic;
SIGNAL count : std_logic_vector(3 DOWNTO 0);
SIGNAL q1 : std_logic_vector(7 DOWNTO 0);

BEGIN

ww_clk <= clk;
ww_rst <= rst;
q <= ww_q;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\rst~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \rst~combout\);

\clk~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);

\Selector7~315_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector7~315\ = q1(1) # count(1) & count(0) & count(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(1),
	datab => q1(1),
	datac => count(0),
	datad => count(2),
	combout => \Selector7~315\);

\Selector2~147_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector2~147\ = \present.s2\ # !\present.s0\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \present.s2\,
	datad => \present.s0\,
	combout => \Selector2~147\);

\clk~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\clk~clkctrl_I\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \clk~clkctrl_I_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~clkctrl\);

\count[0]~207_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \count[0]~207\ = !count(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => count(0),
	combout => \count[0]~207\);

\rst~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_rst,
	combout => \rst~combout\);

\count[0]~204_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \count[0]~204\ = !\rst~combout\ & (\present.s0\ # !\Equal0~110\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s0\,
	datac => \rst~combout\,
	datad => \Equal0~110\,
	combout => \count[0]~204\);

\count[0]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \count[0]~207\,
	ena => \count[0]~204\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count(0));

\count[1]~206_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \count[1]~206\ = count(1) $ (count(0) & \count[0]~204\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => count(0),
	datac => count(1),
	datad => \count[0]~204\,
	combout => \count[1]~206\);

\count[1]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \count[1]~206\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count(1));

\count[2]~205_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \count[2]~205\ = count(2) $ (count(1) & count(0) & \count[0]~204\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(1),
	datab => count(0),
	datac => count(2),
	datad => \count[0]~204\,
	combout => \count[2]~205\);

\count[2]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \count[2]~205\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count(2));

\Equal1~44_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Equal1~44\ = count(1) & count(2) & count(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => count(1),
	datac => count(2),
	datad => count(0),
	combout => \Equal1~44\);

\Selector13~118_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector13~118\ = \Equal1~44\ & !\present.s0\ & (!\Equal0~110\) # !\Equal1~44\ & (\present.s1\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000001110100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s0\,
	datab => \Equal1~44\,
	datac => \present.s1\,
	datad => \Equal0~110\,
	combout => \Selector13~118\);

\rst~clkctrl_I\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \rst~clkctrl_I_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \rst~clkctrl\);

\present.s1~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector13~118\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \present.s1\);

\present.s2~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	sdata => \present.s1\,
	aclr => \rst~clkctrl\,
	sload => VCC,
	ena => \Equal1~44\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \present.s2\);

\present.s3~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	sdata => \present.s2\,
	aclr => \rst~clkctrl\,
	sload => VCC,
	ena => \Equal1~44\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \present.s3\);

\q1[3]~431_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1[3]~431\ = !\present.s2\ & !\present.s3\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \present.s2\,
	datad => \present.s3\,
	combout => \q1[3]~431\);

\Selector12~126_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector12~126\ = \Equal1~44\ & !\present.s3\ & (\present.s0\ # !\Equal0~110\) # !\Equal1~44\ & (\present.s0\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000001110100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s3\,
	datab => \Equal1~44\,
	datac => \present.s0\,
	datad => \Equal0~110\,
	combout => \Selector12~126\);

\present.s0~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector12~126\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \present.s0\);

\q1[1]~428_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1[1]~428\ = \present.s3\ # !\present.s0\ & !\Equal0~110\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s3\,
	datac => \present.s0\,
	datad => \Equal0~110\,
	combout => \q1[1]~428\);

\Selector6~133_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector6~133\ = !\Equal1~44\ & (\q1[1]~428\ & (q1(2)) # !\q1[1]~428\ & q1(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Equal1~44\,
	datab => q1(0),
	datac => q1(2),
	datad => \q1[1]~428\,
	combout => \Selector6~133\);

\q1[1]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector6~133\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(1));

\Selector5~133_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector5~133\ = !\Equal1~44\ & (\q1[1]~428\ & (q1(3)) # !\q1[1]~428\ & q1(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Equal1~44\,
	datab => q1(1),
	datac => q1(3),
	datad => \q1[1]~428\,
	combout => \Selector5~133\);

\q1[2]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \Selector5~133\,
	aclr => \rst~clkctrl\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => q1(2));

\q1~430_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1~430\ = q1(2) & (!count(1) # !count(0) # !count(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(2),
	datab => q1(2),
	datac => count(0),
	datad => count(1),
	combout => \q1~430\);

\q1~432_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1~432\ = q1(0) & (!count(1) # !count(2) # !count(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => q1(0),
	datab => count(0),
	datac => count(2),
	datad => count(1),
	combout => \q1~432\);

\q1[3]~434_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1[3]~434\ = \present.s3\ # \present.s1\ & !\present.s2\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111010101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s3\,
	datab => \present.s1\,
	datac => \present.s2\,
	combout => \q1[3]~434\);

\q1[3]~433_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \q1[3]~433\ = \present.s3\ # \present.s2\ & !\Equal1~44\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s2\,
	datac => \present.s3\,
	datad => \Equal1~44\,
	combout => \q1[3]~433\);

\Selector4~59_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector4~59\ = \q1[3]~434\ & (\q1~432\ & \q1[3]~433\) # !\q1[3]~434\ & (q1(2) # !\q1[3]~433\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100101000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => q1(2),
	datab => \q1~432\,
	datac => \q1[3]~434\,
	datad => \q1[3]~433\,
	combout => \Selector4~59\);

\Selector4~60_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector4~60\ = \q1[3]~431\ & (\Selector4~59\ & \q1~429\ # !\Selector4~59\ & (\q1~430\)) # !\q1[3]~431\ & (\Selector4~59\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \q1~429\,
	datab => \q1[3]~431\,
	datac => \q1~430\,
	datad => \Selector4~59\,
	combout => \Selector4~60\);

\Selector4~61_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector4~61\ = \Selector4~60\ & (\present.s1\ # !\q1[3]~431\ # !\Equal0~110\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \present.s1\,
	datab => \Equal0~110\,
	datac => \q1[3]~431\,
	datad => \Selector4~60\,
	combout => \Selector4~61\);

\q1[3]~I\ : cycloneii_lcell_ff
PORT MAP (
12

led.vho - 源码说明

本页面展示了「大量VHDL写的数字系统设计有用实例达到」中的 led.vho 源码文件，采用 VHO 编程语言编写，共 1,170 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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