cymometer.tan.summary

来自「大量VHDL写的数字系统设计有用实例达到」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.510 ns
From           : seg7[6]$latch
To             : seg7[6]
From Clock     : sysclk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clkin'
Slack          : N/A
Required Time  : None
Actual Time    : 137.42 MHz ( period = 7.277 ns )
From           : cntp2[0]
To             : cntp4[3]
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Setup: 'sysclk'
Slack          : N/A
Required Time  : None
Actual Time    : 196.81 MHz ( period = 5.081 ns )
From           : cnt[0]
To             : cnt[24]
From Clock     : sysclk
To Clock       : sysclk
Failed Paths   : 0

Type           : Clock Hold: 'sysclk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : cnt[13]
To             : seg7[1]$latch
From Clock     : sysclk
To Clock       : sysclk
Failed Paths   : 21

Type           : Clock Hold: 'clkin'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : cntq3[3]
To             : seg7[3]$latch
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 200

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 221

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