pll.fit.rpt

大量VHDL写的数字系统设计有用实例达到

; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; nCEO                                         ; As output driving ground ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                         ;
+------------------------------------------------------------------+------------+
; Name                                                             ; Value      ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                 ; ff         ;
; Mid Wire Use - Fit Attempt 1                                     ; 0          ;
; Mid Slack - Fit Attempt 1                                        ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                              ; 1          ;
; LE/ALM Count - Fit Attempt 1                                     ; 1          ;
; LAB Count - Fit Attempt 1                                        ; 1          ;
; Outputs per Lab - Fit Attempt 1                                  ; 0.000      ;
; Inputs per LAB - Fit Attempt 1                                   ; 0.000      ;
; Global Inputs per LAB - Fit Attempt 1                            ; 0.000      ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1    ; 0:1        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1             ; 0:1        ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1               ; 0:1        ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1       ; 0:1        ;
; LAB Constraint 'global controls' - Fit Attempt 1                 ; 0:1        ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:1        ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:1        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1      ; 0:1        ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1                 ; 0:1        ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1          ; 0:1        ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1      ; 0:1        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1        ; 0:1        ;
; LEs in Chains - Fit Attempt 1                                    ; 0          ;
; LEs in Long Chains - Fit Attempt 1                               ; 0          ;
; LABs with Chains - Fit Attempt 1                                 ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                        ; 0          ;
; Time - Fit Attempt 1                                             ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1                              ; 0.016      ;
+------------------------------------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Placement                       ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 3 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff         ;
; Mid Wire Use - Fit Attempt 1       ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000      ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Routing                          ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Early Wire Use - Fit Attempt 1      ; 0          ;
; Peak Regional Wire - Fit Attempt 1  ; 0          ;
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015      ;
+-------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 25 20:18:02 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pll -c pll
Info: Selected device EP2C8T144C8 for design "pll"
Info: Implemented PLL "altpll:altpll_component|pll" as Cyclone II PLL type
    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component|_clk0 port
    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component|_clk1 port
    Info: Implementing clock multiplication of 6, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component|_clk2 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 7 of 7 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 6 pins of 6 total pins
    Info: Pin c0 not assigned to an exact location on the device
    Info: Pin c1 not assigned to an exact location on the device
    Info: Pin c2 not assigned to an exact location on the device
    Info: Pin locked not assigned to an exact location on the device
    Info: Pin areset not assigned to an exact location on the device