lpm_ram.tan.rpt

大量VHDL写的数字系统设计有用实例达到

    Info: Processing started: Mon Apr 23 10:25:56 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lpm_ram -c lpm_ram --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 163.03 MHz between source memory "altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg" and destination memory "altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]"
    Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 3.641 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg'
            Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]'
            Info: Total cell delay = 3.641 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.020 ns
            Info: + Shortest clock path from clock "clock" to destination memory is 2.873 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.829 ns) + CELL(0.815 ns) = 2.873 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]'
                Info: Total cell delay = 1.905 ns ( 66.31 % )
                Info: Total interconnect delay = 0.968 ns ( 33.69 % )
            Info: - Longest clock path from clock "clock" to source memory is 2.893 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.829 ns) + CELL(0.835 ns) = 2.893 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg'
                Info: Total cell delay = 1.925 ns ( 66.54 % )
                Info: Total interconnect delay = 0.968 ns ( 33.46 % )
        Info: + Micro clock to output delay of source is 0.260 ns
        Info: + Micro setup delay of destination is 0.046 ns
Info: tsu for memory "altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg" (data pin = "wren", clock pin = "clock") is 5.486 ns
    Info: + Longest pin to memory delay is 8.333 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'wren'
        Info: 2: + IC(7.015 ns) + CELL(0.384 ns) = 8.333 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg'
        Info: Total cell delay = 1.318 ns ( 15.82 % )
        Info: Total interconnect delay = 7.015 ns ( 84.18 % )
    Info: + Micro setup delay of destination is 0.046 ns
    Info: - Shortest clock path from clock "clock" to destination memory is 2.893 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.829 ns) + CELL(0.835 ns) = 2.893 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg'
        Info: Total cell delay = 1.925 ns ( 66.54 % )
        Info: Total interconnect delay = 0.968 ns ( 33.46 % )
Info: tco from clock "clock" to destination pin "q[6]" through memory "altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]" is 9.918 ns
    Info: + Longest clock path from clock "clock" to source memory is 2.873 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.829 ns) + CELL(0.815 ns) = 2.873 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]'
        Info: Total cell delay = 1.905 ns ( 66.31 % )
        Info: Total interconnect delay = 0.968 ns ( 33.69 % )
    Info: + Micro clock to output delay of source is 0.260 ns
    Info: + Longest memory to pin delay is 6.785 ns
        Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X27_Y12; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]'
        Info: 2: + IC(3.620 ns) + CELL(3.056 ns) = 6.785 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q[6]'
        Info: Total cell delay = 3.165 ns ( 46.65 % )
        Info: Total interconnect delay = 3.620 ns ( 53.35 % )
Info: th for memory "altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4" (data pin = "address[4]", clock pin = "clock") is 0.260 ns
    Info: + Longest clock path from clock "clock" to destination memory is 2.893 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.829 ns) + CELL(0.835 ns) = 2.893 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4'
        Info: Total cell delay = 1.925 ns ( 66.54 % )
        Info: Total interconnect delay = 0.968 ns ( 33.46 % )
    Info: + Micro hold delay of destination is 0.267 ns
    Info: - Shortest pin to memory delay is 2.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 1; PIN Node = 'address[4]'
        Info: 2: + IC(1.624 ns) + CELL(0.176 ns) = 2.900 ns; Loc. = M4K_X27_Y12; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4'
        Info: Total cell delay = 1.276 ns ( 44.00 % )
        Info: Total interconnect delay = 1.624 ns ( 56.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Mon Apr 23 10:25:58 2007
    Info: Elapsed time: 00:00:02