lpm_ram.tan.rpt

大量VHDL写的数字系统设计有用实例达到

; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg5  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a5~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg6  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a6~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg7  ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a7~porta_memory_reg0 ; clock      ; clock    ; None                        ; None                      ; 2.931 ns                ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                        ;
+-------+--------------+------------+------------+------------------------------------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From       ; To                                                                                             ; To Clock ;
+-------+--------------+------------+------------+------------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 5.486 ns   ; wren       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; clock    ;
; N/A   ; None         ; 5.312 ns   ; address[1] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; clock    ;
; N/A   ; None         ; 5.291 ns   ; address[2] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; clock    ;
; N/A   ; None         ; 5.006 ns   ; data[5]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg5  ; clock    ;
; N/A   ; None         ; 4.944 ns   ; data[3]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg3  ; clock    ;
; N/A   ; None         ; 4.932 ns   ; data[7]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg7  ; clock    ;
; N/A   ; None         ; 4.903 ns   ; data[4]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg4  ; clock    ;
; N/A   ; None         ; 4.634 ns   ; data[6]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg6  ; clock    ;
; N/A   ; None         ; 4.620 ns   ; data[0]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0  ; clock    ;
; N/A   ; None         ; 4.415 ns   ; address[0] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; clock    ;
; N/A   ; None         ; 0.458 ns   ; address[3] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; clock    ;
; N/A   ; None         ; 0.115 ns   ; data[2]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg2  ; clock    ;
; N/A   ; None         ; 0.101 ns   ; data[1]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1  ; clock    ;
; N/A   ; None         ; 0.053 ns   ; address[4] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; clock    ;
+-------+--------------+------------+------------+------------------------------------------------------------------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                           ;
+-------+--------------+------------+-----------------------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                  ; To   ; From Clock ;
+-------+--------------+------------+-----------------------------------------------------------------------+------+------------+
; N/A   ; None         ; 9.918 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] ; q[6] ; clock      ;
; N/A   ; None         ; 8.849 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2] ; q[2] ; clock      ;
; N/A   ; None         ; 8.623 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7] ; q[7] ; clock      ;
; N/A   ; None         ; 8.516 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5] ; q[5] ; clock      ;
; N/A   ; None         ; 8.486 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1] ; q[1] ; clock      ;
; N/A   ; None         ; 7.980 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3] ; q[3] ; clock      ;
; N/A   ; None         ; 7.769 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] ; q[0] ; clock      ;
; N/A   ; None         ; 7.625 ns   ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4] ; q[4] ; clock      ;
+-------+--------------+------------+-----------------------------------------------------------------------+------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                               ;
+---------------+-------------+-----------+------------+------------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                                                                                             ; To Clock ;
+---------------+-------------+-----------+------------+------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; 0.260 ns  ; address[4] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; clock    ;
; N/A           ; None        ; 0.212 ns  ; data[1]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1  ; clock    ;
; N/A           ; None        ; 0.198 ns  ; data[2]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg2  ; clock    ;
; N/A           ; None        ; -0.145 ns ; address[3] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; clock    ;
; N/A           ; None        ; -4.102 ns ; address[0] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; clock    ;
; N/A           ; None        ; -4.307 ns ; data[0]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0  ; clock    ;
; N/A           ; None        ; -4.321 ns ; data[6]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg6  ; clock    ;
; N/A           ; None        ; -4.590 ns ; data[4]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg4  ; clock    ;
; N/A           ; None        ; -4.619 ns ; data[7]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg7  ; clock    ;
; N/A           ; None        ; -4.631 ns ; data[3]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg3  ; clock    ;
; N/A           ; None        ; -4.693 ns ; data[5]    ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg5  ; clock    ;
; N/A           ; None        ; -4.978 ns ; address[2] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; clock    ;
; N/A           ; None        ; -4.999 ns ; address[1] ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; clock    ;
; N/A           ; None        ; -5.173 ns ; wren       ; altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; clock    ;
+---------------+-------------+-----------+------------+------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version