elevator.fit.smsg

大量VHDL写的数字系统设计有用实例达到

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Apr 21 15:10:10 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off elevator -c elevator
Info: Selected device EP2C8T144C8 for design "elevator"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 206 of 206 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 40 pins of 40 total pins
    Info: Pin door[0] not assigned to an exact location on the device
    Info: Pin door[1] not assigned to an exact location on the device
    Info: Pin led[0] not assigned to an exact location on the device
    Info: Pin led[1] not assigned to an exact location on the device
    Info: Pin led[2] not assigned to an exact location on the device
    Info: Pin led[3] not assigned to an exact location on the device
    Info: Pin led[4] not assigned to an exact location on the device
    Info: Pin led[5] not assigned to an exact location on the device
    Info: Pin led[6] not assigned to an exact location on the device
    Info: Pin ud not assigned to an exact location on the device
    Info: Pin alarm not assigned to an exact location on the device
    Info: Pin up not assigned to an exact location on the device
    Info: Pin down not assigned to an exact location on the device
    Info: Pin full not assigned to an exact location on the device
    Info: Pin stop not assigned to an exact location on the device
    Info: Pin close not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin clr not assigned to an exact location on the device
    Info: Pin g1 not assigned to an exact location on the device
    Info: Pin g4 not assigned to an exact location on the device
    Info: Pin g3 not assigned to an exact location on the device
    Info: Pin g5 not assigned to an exact location on the device
    Info: Pin g6 not assigned to an exact location on the device
    Info: Pin g2 not assigned to an exact location on the device
    Info: Pin up1 not assigned to an exact location on the device
    Info: Pin k3 not assigned to an exact location on the device
    Info: Pin k1 not assigned to an exact location on the device
    Info: Pin k2 not assigned to an exact location on the device
    Info: Pin k5 not assigned to an exact location on the device
    Info: Pin k4 not assigned to an exact location on the device
    Info: Pin up3 not assigned to an exact location on the device
    Info: Pin up2 not assigned to an exact location on the device
    Info: Pin up5 not assigned to an exact location on the device
    Info: Pin up4 not assigned to an exact location on the device
    Info: Pin down6 not assigned to an exact location on the device
    Info: Pin down4 not assigned to an exact location on the device
    Info: Pin down2 not assigned to an exact location on the device
    Info: Pin down3 not assigned to an exact location on the device
    Info: Pin down5 not assigned to an exact location on the device
    Info: Pin k6 not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 39 (unused VREF, 3.30 VCCIO, 26 input, 13 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 6.594 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y11; Fanout = 4; REG Node = 'k55'
    Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X17_Y11; Fanout = 4; COMB Node = 'en_down~1621'
    Info: 3: + IC(0.160 ns) + CELL(0.647 ns) = 1.688 ns; Loc. = LAB_X17_Y11; Fanout = 4; COMB Node = 'opendoor~2131'
    Info: 4: + IC(0.160 ns) + CELL(0.646 ns) = 2.494 ns; Loc. = LAB_X17_Y11; Fanout = 6; COMB Node = 'LessThan3~77'
    Info: 5: + IC(0.935 ns) + CELL(0.624 ns) = 4.053 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1625'
    Info: 6: + IC(0.160 ns) + CELL(0.651 ns) = 4.864 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1628'
    Info: 7: + IC(0.187 ns) + CELL(0.624 ns) = 5.675 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1630'
    Info: 8: + IC(0.160 ns) + CELL(0.651 ns) = 6.486 ns; Loc. = LAB_X17_Y12; Fanout = 1; COMB Node = 'en_down~1631'
    Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 6.594 ns; Loc. = LAB_X17_Y12; Fanout = 6; REG Node = 'en_down'
    Info: Total cell delay = 4.321 ns ( 65.53 % )
    Info: Total interconnect delay = 2.273 ns ( 34.47 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 13 output pins without output pin load capacitance assignment
    Info: Pin "door[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "door[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ud" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "alarm" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "up" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "down" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Sat Apr 21 15:10:21 2007
    Info: Elapsed time: 00:00:11