📄 decoder.tan.qmsg

📁 大量VHDL写的数字系统设计有用实例达到
💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock \"clk1khz\" as buffer" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 13 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk20mhz register comb1\[1\] register m_hun\[1\] 146.48 MHz 6.827 ns Internal " "Info: Clock \"clk20mhz\" has Internal fmax of 146.48 MHz between source register \"comb1\[1\]\" and destination register \"m_hun\[1\]\" (period= 6.827 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.565 ns + Longest register register " "Info: + Longest register to register delay is 6.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns comb1\[1\] 1 REG LCFF_X19_Y12_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y12_N3; Fanout = 5; REG Node = 'comb1\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { comb1[1] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.623 ns) 1.084 ns Equal3~146 2 COMB LCCOMB_X19_Y12_N26 1 " "Info: 2: + IC(0.461 ns) + CELL(0.623 ns) = 1.084 ns; Loc. = LCCOMB_X19_Y12_N26; Fanout = 1; COMB Node = 'Equal3~146'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.084 ns" { comb1[1] Equal3~146 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.414 ns) + CELL(0.614 ns) 3.112 ns Equal3~149 3 COMB LCCOMB_X22_Y12_N30 3 " "Info: 3: + IC(1.414 ns) + CELL(0.614 ns) = 3.112 ns; Loc. = LCCOMB_X22_Y12_N30; Fanout = 3; COMB Node = 'Equal3~149'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.028 ns" { Equal3~146 Equal3~149 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.596 ns) + CELL(0.624 ns) 4.332 ns m_one\[3\]~27 4 COMB LCCOMB_X21_Y12_N30 16 " "Info: 4: + IC(0.596 ns) + CELL(0.624 ns) = 4.332 ns; Loc. = LCCOMB_X21_Y12_N30; Fanout = 16; COMB Node = 'm_one\[3\]~27'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.220 ns" { Equal3~149 m_one[3]~27 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.378 ns) + CELL(0.855 ns) 6.565 ns m_hun\[1\] 5 REG LCFF_X22_Y11_N9 1 " "Info: 5: + IC(1.378 ns) + CELL(0.855 ns) = 6.565 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 1; REG Node = 'm_hun\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.233 ns" { m_one[3]~27 m_hun[1] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.716 ns ( 41.37 % ) " "Info: Total cell delay = 2.716 ns ( 41.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.849 ns ( 58.63 % ) " "Info: Total interconnect delay = 3.849 ns ( 58.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { comb1[1] Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { comb1[1] Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } { 0.000ns 0.461ns 1.414ns 0.596ns 1.378ns } { 0.000ns 0.623ns 0.614ns 0.624ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20mhz destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk20mhz\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk20mhz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk20mhz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk20mhz } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk20mhz~clkctrl 2 COMB CLKCTRL_G2 91 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 91; COMB Node = 'clk20mhz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk20mhz clk20mhz~clkctrl } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.782 ns m_hun\[1\] 3 REG LCFF_X22_Y11_N9 1 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 1; REG Node = 'm_hun\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.12 % ) " "Info: Total cell delay = 1.756 ns ( 63.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 36.88 % ) " "Info: Total interconnect delay = 1.026 ns ( 36.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk20mhz clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl m_hun[1] } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20mhz source 2.780 ns - Longest register " "Info: - Longest clock path from clock \"clk20mhz\" to source register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk20mhz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk20mhz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk20mhz } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk20mhz~clkctrl 2 COMB CLKCTRL_G2 91 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 91; COMB Node = 'clk20mhz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk20mhz clk20mhz~clkctrl } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.885 ns) + CELL(0.666 ns) 2.780 ns comb1\[1\] 3 REG LCFF_X19_Y12_N3 5 " "Info: 3: + IC(0.885 ns) + CELL(0.666 ns) = 2.780 ns; Loc. = LCFF_X19_Y12_N3; Fanout = 5; REG Node = 'comb1\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { clk20mhz~clkctrl comb1[1] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.17 % ) " "Info: Total cell delay = 1.756 ns ( 63.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 36.83 % ) " "Info: Total interconnect delay = 1.024 ns ( 36.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.780 ns" { clk20mhz clk20mhz~clkctrl comb1[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.780 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl comb1[1] } { 0.000ns 0.000ns 0.139ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk20mhz clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl m_hun[1] } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.780 ns" { clk20mhz clk20mhz~clkctrl comb1[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.780 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl comb1[1] } { 0.000ns 0.000ns 0.139ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { comb1[1] Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { comb1[1] Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } { 0.000ns 0.461ns 1.414ns 0.596ns 1.378ns } { 0.000ns 0.623ns 0.614ns 0.624ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk20mhz clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl m_hun[1] } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.780 ns" { clk20mhz clk20mhz~clkctrl comb1[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.780 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl comb1[1] } { 0.000ns 0.000ns 0.139ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "m_hun\[1\] money_in\[9\] clk20mhz 11.457 ns register " "Info: tsu for register \"m_hun\[1\]\" (data pin = \"money_in\[9\]\", clock pin = \"clk20mhz\") is 11.457 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.279 ns + Longest pin register " "Info: + Longest pin to register delay is 14.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns money_in\[9\] 1 PIN PIN_103 3 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_103; Fanout = 3; PIN Node = 'money_in\[9\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { money_in[9] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.493 ns) + CELL(0.370 ns) 8.798 ns Equal3~146 2 COMB LCCOMB_X19_Y12_N26 1 " "Info: 2: + IC(7.493 ns) + CELL(0.370 ns) = 8.798 ns; Loc. = LCCOMB_X19_Y12_N26; Fanout = 1; COMB Node = 'Equal3~146'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.863 ns" { money_in[9] Equal3~146 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.414 ns) + CELL(0.614 ns) 10.826 ns Equal3~149 3 COMB LCCOMB_X22_Y12_N30 3 " "Info: 3: + IC(1.414 ns) + CELL(0.614 ns) = 10.826 ns; Loc. = LCCOMB_X22_Y12_N30; Fanout = 3; COMB Node = 'Equal3~149'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.028 ns" { Equal3~146 Equal3~149 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.596 ns) + CELL(0.624 ns) 12.046 ns m_one\[3\]~27 4 COMB LCCOMB_X21_Y12_N30 16 " "Info: 4: + IC(0.596 ns) + CELL(0.624 ns) = 12.046 ns; Loc. = LCCOMB_X21_Y12_N30; Fanout = 16; COMB Node = 'm_one\[3\]~27'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.220 ns" { Equal3~149 m_one[3]~27 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.378 ns) + CELL(0.855 ns) 14.279 ns m_hun\[1\] 5 REG LCFF_X22_Y11_N9 1 " "Info: 5: + IC(1.378 ns) + CELL(0.855 ns) = 14.279 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 1; REG Node = 'm_hun\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.233 ns" { m_one[3]~27 m_hun[1] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.398 ns ( 23.80 % ) " "Info: Total cell delay = 3.398 ns ( 23.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.881 ns ( 76.20 % ) " "Info: Total interconnect delay = 10.881 ns ( 76.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "14.279 ns" { money_in[9] Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "14.279 ns" { money_in[9] money_in[9]~combout Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } { 0.000ns 0.000ns 7.493ns 1.414ns 0.596ns 1.378ns } { 0.000ns 0.935ns 0.370ns 0.614ns 0.624ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20mhz destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk20mhz\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk20mhz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk20mhz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk20mhz } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk20mhz~clkctrl 2 COMB CLKCTRL_G2 91 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 91; COMB Node = 'clk20mhz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk20mhz clk20mhz~clkctrl } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.782 ns m_hun\[1\] 3 REG LCFF_X22_Y11_N9 1 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 1; REG Node = 'm_hun\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.12 % ) " "Info: Total cell delay = 1.756 ns ( 63.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 36.88 % ) " "Info: Total interconnect delay = 1.026 ns ( 36.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk20mhz clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl m_hun[1] } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "14.279 ns" { money_in[9] Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "14.279 ns" { money_in[9] money_in[9]~combout Equal3~146 Equal3~149 m_one[3]~27 m_hun[1] } { 0.000ns 0.000ns 7.493ns 1.414ns 0.596ns 1.378ns } { 0.000ns 0.935ns 0.370ns 0.614ns 0.624ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk20mhz clk20mhz~clkctrl m_hun[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl m_hun[1] } { 0.000ns 0.000ns 0.139ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk20mhz seg7\[2\] cnt\[2\] 18.700 ns register " "Info: tco from clock \"clk20mhz\" to destination pin \"seg7\[2\]\" through register \"cnt\[2\]\" is 18.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk20mhz source 5.388 ns + Longest register " "Info: + Longest clock path from clock \"clk20mhz\" to source register is 5.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk20mhz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk20mhz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk20mhz } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk20mhz~clkctrl 2 COMB CLKCTRL_G2 91 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 91; COMB Node = 'clk20mhz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk20mhz clk20mhz~clkctrl } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.970 ns) 3.079 ns clk1khz 3 REG LCFF_X33_Y10_N7 2 " "Info: 3: + IC(0.880 ns) + CELL(0.970 ns) = 3.079 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { clk20mhz~clkctrl clk1khz } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.000 ns) 3.835 ns clk1khz~clkctrl 4 COMB CLKCTRL_G6 3 " "Info: 4: + IC(0.756 ns) + CELL(0.000 ns) = 3.835 ns; Loc. = CLKCTRL_G6; Fanout = 3; COMB Node = 'clk1khz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.756 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 5.388 ns cnt\[2\] 5 REG LCFF_X22_Y11_N17 22 " "Info: 5: + IC(0.887 ns) + CELL(0.666 ns) = 5.388 ns; Loc. = LCFF_X22_Y11_N17; Fanout = 22; REG Node = 'cnt\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk1khz~clkctrl cnt[2] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 112 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 50.59 % ) " "Info: Total cell delay = 2.726 ns ( 50.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.662 ns ( 49.41 % ) " "Info: Total interconnect delay = 2.662 ns ( 49.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.388 ns" { clk20mhz clk20mhz~clkctrl clk1khz clk1khz~clkctrl cnt[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.388 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl clk1khz clk1khz~clkctrl cnt[2] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 112 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.008 ns + Longest register pin " "Info: + Longest register to pin delay is 13.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[2\] 1 REG LCFF_X22_Y11_N17 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y11_N17; Fanout = 22; REG Node = 'cnt\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[2] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 112 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.522 ns) + CELL(0.651 ns) 2.173 ns Mux1~39 2 COMB LCCOMB_X18_Y11_N12 1 " "Info: 2: + IC(1.522 ns) + CELL(0.651 ns) = 2.173 ns; Loc. = LCCOMB_X18_Y11_N12; Fanout = 1; COMB Node = 'Mux1~39'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.173 ns" { cnt[2] Mux1~39 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.651 ns) 3.903 ns Mux1~40 3 COMB LCCOMB_X21_Y11_N10 1 " "Info: 3: + IC(1.079 ns) + CELL(0.651 ns) = 3.903 ns; Loc. = LCCOMB_X21_Y11_N10; Fanout = 1; COMB Node = 'Mux1~40'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.730 ns" { Mux1~39 Mux1~40 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.651 ns) 5.604 ns Mux1~41 4 COMB LCCOMB_X19_Y11_N10 7 " "Info: 4: + IC(1.050 ns) + CELL(0.651 ns) = 5.604 ns; Loc. = LCCOMB_X19_Y11_N10; Fanout = 7; COMB Node = 'Mux1~41'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.701 ns" { Mux1~40 Mux1~41 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(0.366 ns) 8.224 ns Mux17~13 5 COMB LCCOMB_X7_Y15_N12 1 " "Info: 5: + IC(2.254 ns) + CELL(0.366 ns) = 8.224 ns; Loc. = LCCOMB_X7_Y15_N12; Fanout = 1; COMB Node = 'Mux17~13'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.620 ns" { Mux1~41 Mux17~13 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.728 ns) + CELL(3.056 ns) 13.008 ns seg7\[2\] 6 PIN PIN_8 0 " "Info: 6: + IC(1.728 ns) + CELL(3.056 ns) = 13.008 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'seg7\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.784 ns" { Mux17~13 seg7[2] } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.375 ns ( 41.32 % ) " "Info: Total cell delay = 5.375 ns ( 41.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.633 ns ( 58.68 % ) " "Info: Total interconnect delay = 7.633 ns ( 58.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.008 ns" { cnt[2] Mux1~39 Mux1~40 Mux1~41 Mux17~13 seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "13.008 ns" { cnt[2] Mux1~39 Mux1~40 Mux1~41 Mux17~13 seg7[2] } { 0.000ns 1.522ns 1.079ns 1.050ns 2.254ns 1.728ns } { 0.000ns 0.651ns 0.651ns 0.651ns 0.366ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.388 ns" { clk20mhz clk20mhz~clkctrl clk1khz clk1khz~clkctrl cnt[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.388 ns" { clk20mhz clk20mhz~combout clk20mhz~clkctrl clk1khz clk1khz~clkctrl cnt[2] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.887ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.008 ns" { cnt[2] Mux1~39 Mux1~40 Mux1~41 Mux17~13 seg7[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "13.008 ns" { cnt[2] Mux1~39 Mux1~40 Mux1~41 Mux17~13 seg7[2] } { 0.000ns 1.522ns 1.079ns 1.050ns 2.254ns 1.728ns } { 0.000ns 0.651ns 0.651ns 0.651ns 0.366ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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