sin.tan.summary

大量VHDL写的数字系统设计有用实例达到

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.061 ns
From           : sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3]
To             : q[3]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 180.05 MHz ( period = 5.554 ns )
From           : sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5
To             : sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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