sin.tan.qmsg

大量VHDL写的数字系统设计有用实例达到

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock memory memory sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|ram_block1a0~porta_address_reg0 sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[0\] 180.05 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 180.05 MHz between source memory \"sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.777 ns 2.777 ns 5.554 ns " "Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X11_Y2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y2; Fanout = 8; MEM Node = 'sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[0\] 2 MEM M4K_X11_Y2 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.900 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 -80 88 144 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 -80 88 144 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.815 ns) 2.900 ns sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[0\] 3 MEM M4K_X11_Y2 1 " "Info: 3: + IC(0.856 ns) + CELL(0.815 ns) = 2.900 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.671 ns" { clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 65.69 % ) " "Info: Total cell delay = 1.905 ns ( 65.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 34.31 % ) " "Info: Total interconnect delay = 0.995 ns ( 34.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.920 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 -80 88 144 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 -80 88 144 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.835 ns) 2.920 ns sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X11_Y2 8 " "Info: 3: + IC(0.856 ns) + CELL(0.835 ns) = 2.920 ns; Loc. = M4K_X11_Y2; Fanout = 8; MEM Node = 'sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.691 ns" { clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 65.92 % ) " "Info: Total cell delay = 1.925 ns ( 65.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 34.08 % ) " "Info: Total interconnect delay = 0.995 ns ( 34.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.920 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.920 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.920 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.920 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.920 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.920 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[3\] sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[3\] 9.061 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[3\]\" through memory \"sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[3\]\" is 9.061 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.900 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 -80 88 144 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clock~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 -80 88 144 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.815 ns) 2.900 ns sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[3\] 3 MEM M4K_X11_Y2 1 " "Info: 3: + IC(0.856 ns) + CELL(0.815 ns) = 2.900 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.671 ns" { clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 65.69 % ) " "Info: Total cell delay = 1.905 ns ( 65.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 34.31 % ) " "Info: Total interconnect delay = 0.995 ns ( 34.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.901 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.901 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[3\] 1 MEM M4K_X11_Y2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_4871:auto_generated\|q_a\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_4871.tdf" "" { Text "D:/my_eda2/sin/db/altsyncram_4871.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.566 ns) + CELL(3.226 ns) 5.901 ns q\[3\] 2 PIN PIN_132 0 " "Info: 2: + IC(2.566 ns) + CELL(3.226 ns) = 5.901 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'q\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.792 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] q[3] } "NODE_NAME" } } { "sin.bdf" "" { Schematic "D:/my_eda2/sin/sin.bdf" { { 128 528 704 144 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.335 ns ( 56.52 % ) " "Info: Total cell delay = 3.335 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.566 ns ( 43.48 % ) " "Info: Total interconnect delay = 2.566 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.901 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] q[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.901 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] q[3] } { 0.000ns 2.566ns } { 0.109ns 3.226ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { clock clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { clock clock~combout clock~clkctrl sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.901 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] q[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.901 ns" { sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] q[3] } { 0.000ns 2.566ns } { 0.109ns 3.226ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 26 10:49:19 2007 " "Info: Processing ended: Thu Apr 26 10:49:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}