jiao_tong.map.summary

来自「大量VHDL写的数字系统设计有用实例达到」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Fri Jun 01 16:22:50 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : jiao_tong
Top-level Entity Name : jiao_tong
Family : Cyclone II
Total logic elements : 63
    Total combinational functions : 63
    Dedicated logic registers : 20
Total registers : 20
Total pins : 17
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0