one_dimension_fuzzy.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity one_dimension_fuzzy is
port(t_error:in std_logic_vector(9 downto 0);----温差
     flag:in std_logic;               -----------符号位
     ratio:out std_logic_vector(3 downto 0));----输出pwm波占空比数
end;
architecture one of one_dimension_fuzzy is
begin
process(t_error,flag)
begin
  if flag='1' then----E>0
     if t_error>="0001010000" then ---E>5
         ratio<="1000";
     elsif t_error>="0000100000" and (t_error<"0001010000")then ---2<E<5
         ratio<="0110";
     elsif t_error>="0000010000" and (t_error<"0000100000")then ---1<E<2
         ratio<="0100";
     elsif t_error>="0000001000" and (t_error<"0000010000")then ---0.5<E<1
         ratio<="0010";
     elsif t_error>"0000000000" and (t_error<"0000001000")then ---0<E<0.5
         ratio<="0001";
     elsif t_error="0000000000" then ----E=0
         ratio<="0000";
     end if;
  else ratio<="0000";----E<0
  end if;
end process;
end;