clk_div.vhd

大量VHDL写的数字系统设计有用实例达到

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is 
 port(clk20M:in std_logic;------时钟信号20MhZ
      clk500k:out std_logic;----频率信号输出500kHz 
      clk1M:out std_logic;------频率信号输出1MHz 
      clk10k:out std_logic;-----频率信号输出10kHz
      clk100:out std_logic);----频率信号输出100Hz
end;
architecture one of clk_div is
signal clk1M_1:std_logic;
signal clk500k_1:std_logic;
signal clk10k_1:std_logic;
signal clk100_1:std_logic;
begin
----------------------------------20分频产生1MHz时钟
process(clk20M)
variable count:integer range 0 to 9;
begin
if clk20M'event and clk20M='1' then 
  if count=9 then 
	 clk1M_1<=not clk1M_1;
	 count:=0;
  else 
     count:=count+1;
  end if;
end if;
end process;
-------------------------------2分频产生500KHz时钟
process(clk1M_1)
begin
if clk1M_1'event and clk1M_1='1' then 
	 clk500k_1<=not clk500k_1;
  end if;
end process;
---------------------------------50分频产生10KHz时钟
process(clk500k_1)
variable count:integer range 0 to 24;
begin
if clk500k_1'event and clk500k_1='1' then 
  if count=24 then 
	 clk10k_1<=not clk10k_1;
	 count:=0;
  else 
     count:=count+1;
  end if;
end if;
end process;
----------------------------100分频产生100Hz时钟
process(clk10k_1)
variable count:integer range 0 to 49;
begin
if clk10k_1'event and clk10k_1='1' then 
  if count=49 then 
	 clk100_1<=not clk100_1;
	 count:=0;
  else 
     count:=count+1;
  end if;
end if;
end process;
--------------------------------------
clk1M<=clk1M_1;
clk500k<=clk500k_1;
clk10k<=clk10k_1;
clk100<=clk100_1;
end ;