pwm.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pwm is
 port(ctrl:in std_logic_vector(3 downto 0); ----PWM控制信号
      clk:in std_logic;             ------------10KHz时钟信号
      pwm1,pwm2:out std_logic);      ----------双路PWM波输出
end entity;
architecture one of pwm is
signal cnt:std_logic_vector(4 downto 0);--integer range 0 to 19;  --计时变量
signal ctrl1:std_logic_vector(4 downto 0);
begin
ctrl1<='0'& ctrl;
process(clk)------------------------计数器计数
begin
if clk'event and clk='1' then
    if cnt=19 then  cnt<="00000";
    else  cnt<=cnt+1;
    end if;
end if;
end process;
process(clk)-------------pwm1和pwm2的产生
begin
if clk'event and clk='1' then
    if cnt<ctrl1 then                           
            pwm1<='1';
            pwm2<='0';
    elsif ((cnt<10)and (cnt>=ctrl1)) then
            pwm1<='0';
            pwm2<='0';
    elsif ((cnt>=10)and (cnt<ctrl1+10)) then
            pwm1<='0';
            pwm2<='1';
    else pwm1<='0';
         pwm2<='0';
    end if; 
end if;                           
end process;
end one;