seven.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
entity seven is
port(i:in std_logic_vector(3 downto 0);
     y:out std_logic_vector(6 downto 0));
end seven;
architecture one of seven is
begin
process(i)
begin
  case i is
	when"0000"=>y<="1111110";
	when"0001"=>y<="0110000";
	when"0010"=>y<="1101101";
	when"0011"=>y<="1111001";
	when"0100"=>y<="0110011";
	when"0101"=>y<="1011011";
	when"0110"=>y<="1011111";
	when"0111"=>y<="1110000";
	when"1000"=>y<="1111111";
	when"1001"=>y<="1111011";
	when others=>y<="1111111";
  end case;
end process;
end one;