mcbsp_to_spi.v

fpga开发的程序

// -------------------------------------------------------------------------------------------------
// $Header:$
// -------------------------------------------------------------------------------------------------
//
// $Log:$
//
// +FHDR-------------------------------------------------------------------------------------
// Copyright (c) 2005 Founder Communications Technology, Inc.
// All Rights Reserved
//
// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE of Founder Communications Technology.
// The copyright notice above does not evidence any actual or intended
// publication of such source code.
//
// No part of this code may be reproduced, stored in a retrieval system, or
// transmitted, in any form or by any means, electronic, mechanical,
// photocopying, recording, or otherwise, without the prior written
// permission of Founder Communications Technology.
//
// -----------------------------------------------------------------------------------------
// FILE NAME    : McBSP_to_SPI.v
// MODULE NAME  : McBSP_to_SPI
// AUTHOR       : tbai
// -----------------------------------------------------------------------------------------
//
// RELEASE HISTORY
// VERSION    DATE            AUTHOR        DESCRIPTION
// 1.0        2005-04-20      tbai		    Original
// 1.1        2005-04-26      tbai          force SPI ports tied to 0/1 when those are not selected
// -----------------------------------------------------------------------------------------
//
// DESCRIPTION:
// this module is to select which SPI port tying to DSP McBSP
//
// Note:
//	SPI ports:	AD9863	MAX5741		AD7911
// -----------------------------------------------------------------------------------------
// SUBMODULE LIST
//
//
//
//
// -----------------------------------------------------------------------------------------
// PARAMETERS
// PARAM_NAME          RANGE    DESCRIPTION                    DEFAULT    UNITS
//
// -----------------------------------------------------------------------------------------
// -FHDR-------------------------------------------------------------------------------------


module McBSP_to_SPI(	i_rst_n,
						i_SPI_choice,
						i_DSP_FSX0,	i_DSP_CLKX0,i_DSP_DX0,o_DSP_DR0,
						i_AD7911_DOUT,o_AD7911_CS_n,o_AD7911_SCLK,o_AD7911_DIN,
						o_MAX5741_CS_n,o_MAX5741_SCLK,o_MAX5741_DIN,i_clk32fc,
						o_AD9863_SPI_CS,o_AD9863_SPI_CLK,o_AD9863_SPI_DIO,i_AD9863_SPI_SDO,o_AD9863_RESET_n
					);

input		i_rst_n;
input[1:0]	i_SPI_choice;

input		i_DSP_FSX0;
input		i_DSP_CLKX0;
input		i_DSP_DX0;
output		o_DSP_DR0;

input		i_AD7911_DOUT;
output		o_AD7911_CS_n;
output		o_AD7911_SCLK;
output		o_AD7911_DIN;

output		o_MAX5741_CS_n;
output		o_MAX5741_SCLK;
output		o_MAX5741_DIN;
input		i_clk32fc;

output		o_AD9863_SPI_CS;
output		o_AD9863_SPI_CLK;
output		o_AD9863_SPI_DIO;
input		i_AD9863_SPI_SDO;
output		o_AD9863_RESET_n;
/////////////////////////////////////////
wire		i_rst_n;
wire[1:0]	i_SPI_choice;

wire		i_DSP_FSX0;
wire		i_DSP_CLKX0;
wire		i_DSP_DX0;
reg			o_DSP_DR0;

wire		i_AD7911_DOUT;
reg			o_AD7911_CS_n;
reg			o_AD7911_SCLK;
reg			o_AD7911_DIN;

reg			o_MAX5741_CS_n;
reg			o_MAX5741_SCLK;
reg			o_MAX5741_DIN;
wire		i_clk32fc;

reg			o_AD9863_SPI_CS;
reg			o_AD9863_SPI_CLK;
reg			o_AD9863_SPI_DIO;
wire		i_AD9863_SPI_SDO;
wire		o_AD9863_RESET_n;
//-----------------------------------------------------------------

////////////////retouch clk timing for MAX5741------tbai  2005/5/9//////////////////////////////////////
reg[3:0]	MAX5741_cs_delay;

always@(negedge i_rst_n or posedge i_clk32fc)
begin
	if (i_rst_n==1'b0)
	begin
		MAX5741_cs_delay[3:0]<=4'b0000;
	end
	else
	begin
		MAX5741_cs_delay[3:0]<={MAX5741_cs_delay[2:0],i_DSP_FSX0};
	end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(i_SPI_choice or i_DSP_FSX0 or i_DSP_CLKX0 or i_DSP_DX0 or i_AD7911_DOUT or i_AD9863_SPI_SDO or MAX5741_cs_delay)
begin
	case (i_SPI_choice)
		2'b01:		begin
						//AD7911 port connection
						o_AD7911_CS_n = i_DSP_FSX0;
						o_AD7911_SCLK = i_DSP_CLKX0;
						o_AD7911_DIN = i_DSP_DX0;
						o_DSP_DR0 = i_AD7911_DOUT;
						//MAX5741 port
						o_MAX5741_CS_n = 1'b1;
						o_MAX5741_SCLK = 1'b0;
						o_MAX5741_DIN = 1'b0;
						//AD9863 port
						o_AD9863_SPI_CS = 1'b1;
						o_AD9863_SPI_CLK = 1'b0;
						o_AD9863_SPI_DIO = 1'b0;
					end
		2'b10:		begin
						//MAX5741 port connection
						o_MAX5741_CS_n = i_DSP_FSX0;
						o_MAX5741_SCLK = i_DSP_CLKX0 & (~MAX5741_cs_delay[3]);		//tbai 2005/5/9
						o_MAX5741_DIN = i_DSP_DX0;
						o_DSP_DR0 = 1'b0;
						//ad9711 port
						o_AD7911_CS_n = 1'b1;
						o_AD7911_SCLK = 1'b0;
						o_AD7911_DIN = 1'b0;
						//AD9863 port
						o_AD9863_SPI_CS = 1'b1;
						o_AD9863_SPI_CLK = 1'b0;
						o_AD9863_SPI_DIO = 1'b0;
					end
		default:	begin
						//AD9863 port connection
						o_AD9863_SPI_CS = i_DSP_FSX0 | (~i_rst_n);
						o_AD9863_SPI_CLK = i_DSP_CLKX0;
						o_AD9863_SPI_DIO = i_DSP_DX0;
						o_DSP_DR0 = i_AD9863_SPI_SDO;
						//AD7911 port
						o_AD7911_CS_n = 1'b1;
						o_AD7911_SCLK = 1'b0;
						o_AD7911_DIN = 1'b0;
						//MAX5741 port
						o_MAX5741_CS_n = 1'b1;
						o_MAX5741_SCLK = 1'b0;
						o_MAX5741_DIN = 1'b0;
					end
	endcase
end

assign o_AD9863_RESET_n = i_rst_n;
endmodule