ad9863_if_old-2005-5-8.v

fpga开发的程序

module AD9863_if (	i_rst_n,i_clk_32fc,
					i_tx_work,i_rx_work,
					i_qdata,i_idata,o_qdata,o_idata,
					o_clk_4fc,i_rclk,i_tclk,o_tx_nrx,
					o_rx_powerdown,o_tx_powerdown,o_ADC_LOPWR,
					o_tx_addr,o_tx_cs,o_tx_rd,i_tx_data,
					o_rx_addr,o_rx_data,o_rx_cs,o_rx_we,
					o_tx_dsp_int,o_rx_dsp_int
				);

input			i_rst_n;
input			i_clk_32fc;

input			i_tx_work;
input			i_rx_work;

input[11:0]		i_qdata;
input[11:0]		i_idata;
output[11:0]	o_qdata;
output[11:0]	o_idata;

output			o_clk_4fc;
input			i_rclk;
input			i_tclk;
output			o_tx_nrx;

output			o_rx_powerdown;
output			o_tx_powerdown;
output			o_ADC_LOPWR;

output[8:0]		o_tx_addr;
output			o_tx_cs;
output			o_tx_rd;
input[31:0]		i_tx_data;

output[8:0]		o_rx_addr;
output[31:0]	o_rx_data;
output			o_rx_cs;
output			o_rx_we;

output			o_tx_dsp_int;
output			o_rx_dsp_int;
//////////////////////////////////////////////////////////////
wire			i_rst_n;
wire			i_clk_32fc;

wire			i_tx_work;
wire			i_rx_work;

wire[11:0]		i_qdata;
wire[11:0]		i_idata;
wire[11:0]		o_qdata;
wire[11:0]		o_idata;

wire			o_clk_4fc;
wire			i_rclk;
wire			i_tclk;
wire			o_tx_nrx;

wire			o_rx_powerdown;
wire			o_tx_powerdown;
wire			o_ADC_LOPWR;

reg[8:0]		o_tx_addr;
reg				o_tx_cs;
reg				o_tx_rd;
wire[31:0]		i_tx_data;

reg[8:0]		o_rx_addr;
wire[31:0]		o_rx_data;
reg				o_rx_cs;
reg				o_rx_we;

wire			o_tx_dsp_int;
wire			o_rx_dsp_int;
//------------------------------------------------------------
reg[1:0]	work_mode;
wire		clk4fc_up_en;
wire		clk4fc_down_en;
reg[2:0]	clk_div_counter;
reg[1:0]	rx_clk_delay;
reg[1:0]	tx_clk_delay;

//clk 4fc generation
always@(negedge i_rst_n or posedge i_clk_32fc)
begin
	if (i_rst_n==1'b0)
	begin
		clk_div_counter[2:0]<=3'b000;
	end
	else
	begin
		clk_div_counter[2:0]<=clk_div_counter[2:0]+1;
	end
end
assign o_clk_4fc = clk_div_counter[2];

always@(negedge i_rst_n or posedge i_clk_32fc)
begin
	if (i_rst_n==1'b0)
	begin
		rx_clk_delay[1:0]<=2'b00;
		tx_clk_delay[1:0]<=2'b00;
	end
	else
	begin
		rx_clk_delay[1:0]<={rx_clk_delay[0],i_rclk};
		tx_clk_delay[1:0]<={tx_clk_delay[0],i_tclk};
	end
end
assign clk4fc_up_en = (tx_clk_delay[0]==1'b1 && tx_clk_delay[1]==1'b0)? 1'b1 : 1'b0;
assign clk4fc_down_en = (rx_clk_delay[0]==1'b0 && rx_clk_delay[1]==1'b1)? 1'b1 : 1'b0;

//rx and tx mode exchange
always@(negedge i_rst_n or posedge i_clk_32fc)
begin
	if (i_rst_n==1'b0)
	begin
		work_mode[1:0]<=2'b00;
	end
	else
	begin
		if(clk4fc_up_en==1'b1)
		begin
			case({i_tx_work,i_rx_work})
				2'b00:	work_mode[1:0]<=2'b00;
				2'b01:	work_mode[1:0]<=2'b01;
				2'b10:	work_mode[1:0]<=2'b10;
				2'b11:	work_mode[1:0]<=2'b00;
				default:work_mode[1:0]<=2'b00;
			endcase
		end
	end
end
assign o_tx_nrx = (work_mode[1:0]==2'b10)? 1'b1 : 1'b0;

//read and send tx data
always@(negedge i_rst_n or posedge i_clk_32fc)
begin
	if (i_rst_n ==1'b0)
	begin
		o_tx_addr[8:0]<=9'h000;
		o_tx_cs<=1'b0;
		o_tx_rd<=1'b0;
	end
	else
	begin
		if (work_mode[1:0]==2'b10)
		begin
			o_tx_cs<=clk4fc_up_en;
			o_tx_rd<=1'b1;
			if (clk4fc_up_en==1'b1)
			begin
				o_tx_addr[8:0]<=o_tx_addr[8:0]+1;
			end
		end
		else
		begin
			o_tx_addr[8:0]<=9'h000;
			o_tx_cs<=1'b0;
			o_tx_rd<=1'b0;
		end
	end
end
assign o_tx_dsp_int = (o_tx_addr[7:0]==8'hff)? 1'b1 : 1'b0;
assign o_qdata = i_tx_data[27:16];
assign o_idata = i_tx_data[11:0];

//receive and write rx_data
always@(negedge i_rst_n or posedge i_clk_32fc)
begin
	if (i_rst_n ==1'b0)
	begin
		o_rx_addr[8:0]<=9'h000;
		o_rx_cs<=1'b0;
		o_rx_we<=1'b0;
	end
	else
	begin
		if (work_mode[1:0]==2'b01)
		begin
			o_rx_cs<=clk4fc_down_en;
			o_rx_we<=1'b1;
			if (clk4fc_down_en==1'b1)
			begin
				o_rx_addr[8:0]<=o_rx_addr[8:0]+1;
			end
		end
		else
		begin
			o_rx_addr[8:0]<=9'h000;
			o_rx_cs<=1'b0;
			o_rx_we<=1'b0;
		end
	end
end
assign o_rx_dsp_int = (o_rx_addr[7:0]==8'hff)? 1'b1 : 1'b0;
assign o_rx_data = {4'h0,i_qdata[11:0],4'h0,i_idata[11:0]};

//power managament
assign	o_rx_powerdown = 1'b0;
assign	o_tx_powerdown = 1'b0;
assign	o_ADC_LOPWR = 1'b0;
endmodule