crc.v

rfid中crc模块的verilog代码

module crc  (sample_clk,
             syn_global_reset,
             ena_crc,
             q_out_decode,
             q_to_encode_shiftregs,
             ena_crc_send,
             shift_crc_receive,
             crc_shift_1bit,
             receive_crc_check,
             crc_generate_sample,
             begin_encode,
             ena_regs_send,
             crc_out,
             crc_right);
//output ports modified to internal ports:crcreg
             
input sample_clk;
input syn_global_reset;

input ena_crc;


input q_out_decode;

input q_to_encode_shiftregs;


input ena_crc_send;

input receive_crc_check;

input shift_crc_receive;


input crc_shift_1bit;



input crc_generate_sample;
input begin_encode;

input ena_regs_send;

reg [0:15] crcreg;
output crc_out;

output crc_right;

wire xorr,xor4,xor11;
wire a;
wire crc_reg_right;

wire data;
assign data=(receive_crc_check)?q_out_decode:
                            (ena_regs_send)?q_to_encode_shiftregs:1'b0;

assign a=(~ena_crc_send)||receive_crc_check||ena_regs_send;
assign xorr=(a&crcreg[15])^data;
assign xor4=(a&xorr)^crcreg[4];
assign xor11=(a&xorr)^crcreg[11];



assign crc_reg_right=(crcreg==16'b1111_0000_1011_1000)?1'b1:1'b0;
assign crc_right=(ena_crc)?crc_reg_right:1'b0;


wire crcreg_move;
assign crcreg_move=shift_crc_receive||crc_shift_1bit||crc_generate_sample;

assign crc_out=crcreg[15];

//always@(posedge sample_clk)
//begin
//   if(crc_reg_right&&stop)
//     begin
//     crc_right<=1'b1;
//   end
// else
//    begin
//      crc_right<=1'b0;
//    end
//end

//always@(posedge sample_clk)
//begin
//  if(!crc_reg_right&&stop)
//    begin
//      crc_wrong<=1'b1;
//    end
//  else
//    begin
//      crc_wrong<=1'b0;
//    end
//end

wire set_to_origin;
assign set_to_origin=syn_global_reset||begin_encode;


always @(posedge sample_clk)
begin 
   if(set_to_origin)
     begin 
        crcreg[0:15]<=16'b1111_1111_1111_1111;
     end
   else if(crcreg_move)
     begin 
       crcreg[0]<=xorr;
       crcreg[1]<=crcreg[0];
       crcreg[2]<=crcreg[1];
       crcreg[3]<=crcreg[2];
       crcreg[4]<=crcreg[3];
       crcreg[5]<=xor4;
       crcreg[6]<=crcreg[5];
       crcreg[7]<=crcreg[6];
       crcreg[8]<=crcreg[7];
       crcreg[9]<=crcreg[8];
       crcreg[10]<=crcreg[9];
       crcreg[11]<=crcreg[10];
       crcreg[12]<=xor11;
       crcreg[13]<=crcreg[12];
       crcreg[14]<=crcreg[13];
       crcreg[15]<=crcreg[14]; 
     end
end
endmodule