📄 state_machine.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[11\] register state.state2 118.43 MHz 8.444 ns Internal " "Info: Clock \"clk\" has Internal fmax of 118.43 MHz between source register \"cnt\[11\]\" and destination register \"state.state2\" (period= 8.444 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.735 ns + Longest register register " "Info: + Longest register to register delay is 7.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[11\] 1 REG LC_X14_Y9_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N4; Fanout = 3; REG Node = 'cnt\[11\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "" { cnt[11] } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 23 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.010 ns) + CELL(0.511 ns) 2.521 ns reduce_nor~186 2 COMB LC_X15_Y9_N7 1 " "Info: 2: + IC(2.010 ns) + CELL(0.511 ns) = 2.521 ns; Loc. = LC_X15_Y9_N7; Fanout = 1; COMB Node = 'reduce_nor~186'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "2.521 ns" { cnt[11] reduce_nor~186 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.363 ns) + CELL(0.200 ns) 5.084 ns reduce_nor~188 3 COMB LC_X12_Y10_N4 1 " "Info: 3: + IC(2.363 ns) + CELL(0.200 ns) = 5.084 ns; Loc. = LC_X12_Y10_N4; Fanout = 1; COMB Node = 'reduce_nor~188'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "2.563 ns" { reduce_nor~186 reduce_nor~188 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 5.818 ns reduce_nor~0 4 COMB LC_X12_Y10_N5 8 " "Info: 4: + IC(0.534 ns) + CELL(0.200 ns) = 5.818 ns; Loc. = LC_X12_Y10_N5; Fanout = 8; COMB Node = 'reduce_nor~0'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "0.734 ns" { reduce_nor~188 reduce_nor~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(1.243 ns) 7.735 ns state.state2 5 REG LC_X12_Y10_N2 3 " "Info: 5: + IC(0.674 ns) + CELL(1.243 ns) = 7.735 ns; Loc. = LC_X12_Y10_N2; Fanout = 3; REG Node = 'state.state2'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "1.917 ns" { reduce_nor~0 state.state2 } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.154 ns 27.85 % " "Info: Total cell delay = 2.154 ns ( 27.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.581 ns 72.15 % " "Info: Total interconnect delay = 5.581 ns ( 72.15 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "7.735 ns" { cnt[11] reduce_nor~186 reduce_nor~188 reduce_nor~0 state.state2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.735 ns" { cnt[11] reduce_nor~186 reduce_nor~188 reduce_nor~0 state.state2 } { 0.000ns 2.010ns 2.363ns 0.534ns 0.674ns } { 0.000ns 0.511ns 0.200ns 0.200ns 1.243ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 32 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 32; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "" { clk } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns state.state2 2 REG LC_X12_Y10_N2 3 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X12_Y10_N2; Fanout = 3; REG Node = 'state.state2'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "5.588 ns" { clk state.state2 } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk state.state2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout state.state2 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 32 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 32; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "" { clk } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns cnt\[11\] 2 REG LC_X14_Y9_N4 3 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X14_Y9_N4; Fanout = 3; REG Node = 'cnt\[11\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "5.588 ns" { clk cnt[11] } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 23 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk cnt[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout cnt[11] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk state.state2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout state.state2 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk cnt[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout cnt[11] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 23 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "7.735 ns" { cnt[11] reduce_nor~186 reduce_nor~188 reduce_nor~0 state.state2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.735 ns" { cnt[11] reduce_nor~186 reduce_nor~188 reduce_nor~0 state.state2 } { 0.000ns 2.010ns 2.363ns 0.534ns 0.674ns } { 0.000ns 0.511ns 0.200ns 0.200ns 1.243ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk state.state2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout state.state2 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk cnt[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout cnt[11] } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk c\[2\] state.state4 13.024 ns register " "Info: tco from clock \"clk\" to destination pin \"c\[2\]\" through register \"state.state4\" is 13.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 32 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 32; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "" { clk } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns state.state4 2 REG LC_X12_Y10_N6 4 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X12_Y10_N6; Fanout = 4; REG Node = 'state.state4'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "5.588 ns" { clk state.state4 } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk state.state4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout state.state4 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.928 ns + Longest register pin " "Info: + Longest register to pin delay is 5.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.state4 1 REG LC_X12_Y10_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N6; Fanout = 4; REG Node = 'state.state4'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "" { state.state4 } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.965 ns) + CELL(0.914 ns) 1.879 ns reduce_or~17 2 COMB LC_X12_Y10_N8 1 " "Info: 2: + IC(0.965 ns) + CELL(0.914 ns) = 1.879 ns; Loc. = LC_X12_Y10_N8; Fanout = 1; COMB Node = 'reduce_or~17'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "1.879 ns" { state.state4 reduce_or~17 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.727 ns) + CELL(2.322 ns) 5.928 ns c\[2\] 3 PIN PIN_117 0 " "Info: 3: + IC(1.727 ns) + CELL(2.322 ns) = 5.928 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c\[2\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "4.049 ns" { reduce_or~17 c[2] } "NODE_NAME" } "" } } { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns 54.59 % " "Info: Total cell delay = 3.236 ns ( 54.59 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.692 ns 45.41 % " "Info: Total interconnect delay = 2.692 ns ( 45.41 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "5.928 ns" { state.state4 reduce_or~17 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.928 ns" { state.state4 reduce_or~17 c[2] } { 0.000ns 0.965ns 1.727ns } { 0.000ns 0.914ns 2.322ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "6.720 ns" { clk state.state4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout state.state4 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine_cmp.qrpt" Compiler "state_machine" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/db/state_machine.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/" "" "5.928 ns" { state.state4 reduce_or~17 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.928 ns" { state.state4 reduce_or~17 c[2] } { 0.000ns 0.965ns 1.727ns } { 0.000ns 0.914ns 2.322ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 14:09:10 2006 " "Info: Processing ended: Sat Feb 18 14:09:10 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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