state_machine.map.qmsg

硬件描述语言的例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 14:08:54 2006 " "Info: Processing started: Sat Feb 18 14:08:54 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_machine.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file state_machine.v" { { "Info" "ISGN_ENTITY_NAME" "1 state_machine " "Info: Found entity 1: state_machine" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "state_machine " "Info: Elaborating entity \"state_machine\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 state_machine.v(31) " "Warning: Verilog HDL assignment warning at state_machine.v(31): truncated value with size 32 to match size of target (24)" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 state_machine.v(34) " "Warning: Verilog HDL assignment warning at state_machine.v(34): truncated value with size 32 to match size of target (24)" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 34 0 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|state_machine\|state 8 0 " "Info: State machine \"\|state_machine\|state\" contains 8 states and 0 state bits" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|state_machine\|state " "Info: Selected Auto state machine encoding method for state machine \"\|state_machine\|state\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|state_machine\|state " "Info: Encoding result for state machine \"\|state_machine\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state7 " "Info: Encoded state bit \"state.state7\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state1 " "Info: Encoded state bit \"state.state1\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state2 " "Info: Encoded state bit \"state.state2\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state3 " "Info: Encoded state bit \"state.state3\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state4 " "Info: Encoded state bit \"state.state4\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state5 " "Info: Encoded state bit \"state.state5\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state6 " "Info: Encoded state bit \"state.state6\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state0 " "Info: Encoded state bit \"state.state0\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state0 00000000 " "Info: State \"\|state_machine\|state.state0\" uses code string \"00000000\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state6 00000011 " "Info: State \"\|state_machine\|state.state6\" uses code string \"00000011\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state5 00000101 " "Info: State \"\|state_machine\|state.state5\" uses code string \"00000101\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state4 00001001 " "Info: State \"\|state_machine\|state.state4\" uses code string \"00001001\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state3 00010001 " "Info: State \"\|state_machine\|state.state3\" uses code string \"00010001\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state2 00100001 " "Info: State \"\|state_machine\|state.state2\" uses code string \"00100001\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state1 01000001 " "Info: State \"\|state_machine\|state.state1\" uses code string \"01000001\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state7 10000001 " "Info: State \"\|state_machine\|state.state7\" uses code string \"10000001\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] VCC " "Warning: Pin \"en\[1\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] VCC " "Warning: Pin \"en\[2\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] VCC " "Warning: Pin \"en\[3\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] VCC " "Warning: Pin \"en\[4\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] VCC " "Warning: Pin \"en\[5\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] VCC " "Warning: Pin \"en\[6\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] VCC " "Warning: Pin \"en\[7\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "64 " "Info: Implemented 64 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 14:08:56 2006 " "Info: Processing ended: Sat Feb 18 14:08:56 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}