state_machine.tan.rpt

硬件描述语言的例程

; N/A                                     ; 177.46 MHz ( period = 5.635 ns )                    ; cnt[3]  ; cnt[21]      ; clk        ; clk      ; None                        ; None                      ; 4.926 ns                ;
; N/A                                     ; 177.46 MHz ( period = 5.635 ns )                    ; cnt[3]  ; cnt[20]      ; clk        ; clk      ; None                        ; None                      ; 4.926 ns                ;
; N/A                                     ; 177.46 MHz ( period = 5.635 ns )                    ; cnt[3]  ; cnt[19]      ; clk        ; clk      ; None                        ; None                      ; 4.926 ns                ;
; N/A                                     ; 177.46 MHz ( period = 5.635 ns )                    ; cnt[3]  ; cnt[18]      ; clk        ; clk      ; None                        ; None                      ; 4.926 ns                ;
; N/A                                     ; 177.46 MHz ( period = 5.635 ns )                    ; cnt[3]  ; cnt[17]      ; clk        ; clk      ; None                        ; None                      ; 4.926 ns                ;
; N/A                                     ; 177.87 MHz ( period = 5.622 ns )                    ; cnt[3]  ; cnt[23]      ; clk        ; clk      ; None                        ; None                      ; 4.913 ns                ;
; N/A                                     ; 177.87 MHz ( period = 5.622 ns )                    ; cnt[3]  ; cnt[22]      ; clk        ; clk      ; None                        ; None                      ; 4.913 ns                ;
; N/A                                     ; 178.99 MHz ( period = 5.587 ns )                    ; cnt[2]  ; cnt[18]      ; clk        ; clk      ; None                        ; None                      ; 4.878 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+--------------+------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To   ; From Clock ;
+-------+--------------+------------+--------------+------+------------+
; N/A   ; None         ; 13.024 ns  ; state.state4 ; c[2] ; clk        ;
; N/A   ; None         ; 12.909 ns  ; state.state7 ; c[4] ; clk        ;
; N/A   ; None         ; 12.842 ns  ; state.state0 ; c[2] ; clk        ;
; N/A   ; None         ; 12.831 ns  ; state.state0 ; c[1] ; clk        ;
; N/A   ; None         ; 12.699 ns  ; state.state4 ; c[7] ; clk        ;
; N/A   ; None         ; 12.518 ns  ; state.state1 ; c[7] ; clk        ;
; N/A   ; None         ; 12.363 ns  ; state.state1 ; c[4] ; clk        ;
; N/A   ; None         ; 12.361 ns  ; state.state6 ; c[6] ; clk        ;
; N/A   ; None         ; 12.290 ns  ; state.state1 ; c[1] ; clk        ;
; N/A   ; None         ; 12.262 ns  ; state.state5 ; c[2] ; clk        ;
; N/A   ; None         ; 11.951 ns  ; state.state2 ; c[5] ; clk        ;
; N/A   ; None         ; 11.880 ns  ; state.state6 ; c[3] ; clk        ;
; N/A   ; None         ; 11.828 ns  ; state.state5 ; c[6] ; clk        ;
; N/A   ; None         ; 11.816 ns  ; state.state4 ; c[4] ; clk        ;
; N/A   ; None         ; 11.746 ns  ; state.state0 ; c[3] ; clk        ;
; N/A   ; None         ; 11.740 ns  ; state.state6 ; c[2] ; clk        ;
; N/A   ; None         ; 11.740 ns  ; state.state7 ; c[1] ; clk        ;
; N/A   ; None         ; 10.652 ns  ; state.state2 ; c[3] ; clk        ;
+-------+--------------+------------+--------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 14:09:08 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_machine -c state_machine
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 118.43 MHz between source register "cnt[11]" and destination register "state.state2" (period= 8.444 ns)
    Info: + Longest register to register delay is 7.735 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N4; Fanout = 3; REG Node = 'cnt[11]'
        Info: 2: + IC(2.010 ns) + CELL(0.511 ns) = 2.521 ns; Loc. = LC_X15_Y9_N7; Fanout = 1; COMB Node = 'reduce_nor~186'
        Info: 3: + IC(2.363 ns) + CELL(0.200 ns) = 5.084 ns; Loc. = LC_X12_Y10_N4; Fanout = 1; COMB Node = 'reduce_nor~188'
        Info: 4: + IC(0.534 ns) + CELL(0.200 ns) = 5.818 ns; Loc. = LC_X12_Y10_N5; Fanout = 8; COMB Node = 'reduce_nor~0'
        Info: 5: + IC(0.674 ns) + CELL(1.243 ns) = 7.735 ns; Loc. = LC_X12_Y10_N2; Fanout = 3; REG Node = 'state.state2'
        Info: Total cell delay = 2.154 ns ( 27.85 % )
        Info: Total interconnect delay = 5.581 ns ( 72.15 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.720 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X12_Y10_N2; Fanout = 3; REG Node = 'state.state2'
            Info: Total cell delay = 2.050 ns ( 30.51 % )
            Info: Total interconnect delay = 4.670 ns ( 69.49 % )
        Info: - Longest clock path from clock "clk" to source register is 6.720 ns
            Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X14_Y9_N4; Fanout = 3; REG Node = 'cnt[11]'
            Info: Total cell delay = 2.050 ns ( 30.51 % )
            Info: Total interconnect delay = 4.670 ns ( 69.49 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "c[2]" through register "state.state4" is 13.024 ns
    Info: + Longest clock path from clock "clk" to source register is 6.720 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X12_Y10_N6; Fanout = 4; REG Node = 'state.state4'
        Info: Total cell delay = 2.050 ns ( 30.51 % )
        Info: Total interconnect delay = 4.670 ns ( 69.49 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N6; Fanout = 4; REG Node = 'state.state4'
        Info: 2: + IC(0.965 ns) + CELL(0.914 ns) = 1.879 ns; Loc. = LC_X12_Y10_N8; Fanout = 1; COMB Node = 'reduce_or~17'
        Info: 3: + IC(1.727 ns) + CELL(2.322 ns) = 5.928 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c[2]'
        Info: Total cell delay = 3.236 ns ( 54.59 % )
        Info: Total interconnect delay = 2.692 ns ( 45.41 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Feb 18 14:09:10 2006
    Info: Elapsed time: 00:00:02