📄 clock.rpt
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Project Information g:\top1\clock.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/10/2008 14:20:42
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CLOCK
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
clock EP1K30QC208-3 6 37 0 0 0 % 94 5 %
User Pins: 6 37 0
Project Information g:\top1\clock.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K30QC208-3 are preliminary
Project Information g:\top1\clock.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
clock@69 adjust
clock@70 clk1HZ
clock@71 clk2HZ
clock@193 cout24
clock@94 en0
clock@95 en1
clock@96 en2
clock@97 en3
clock@37 en4
clock@160 en5
clock@161 hh0
clock@162 hh1
clock@163 hh2
clock@164 hh3
clock@166 hh4
clock@167 hh5
clock@168 hh6
clock@25 hl0
clock@26 hl1
clock@27 hl2
clock@28 hl3
clock@29 hl4
clock@30 hl5
clock@31 hl6
clock@148 mh0
clock@147 mh1
clock@144 mh2
clock@143 mh3
clock@142 ml0
clock@141 ml1
clock@140 ml2
clock@139 ml3
clock@68 mode
clock@173 reset
clock@136 sh0
clock@135 sh1
clock@134 sh2
clock@133 sh3
clock@132 sl0
clock@131 sl1
clock@128 sl2
clock@127 sl3
clock@187 vcc
Project Information g:\top1\clock.rpt
** FILE HIERARCHY **
|mode_adjust:G1|
|count24:G2|
|count24:G2|lpm_add_sub:115|
|count24:G2|lpm_add_sub:115|addcore:adder|
|count24:G2|lpm_add_sub:115|altshift:result_ext_latency_ffs|
|count24:G2|lpm_add_sub:115|altshift:carry_ext_latency_ffs|
|count24:G2|lpm_add_sub:115|altshift:oflow_ext_latency_ffs|
|count24:G2|lpm_add_sub:144|
|count24:G2|lpm_add_sub:144|addcore:adder|
|count24:G2|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|count24:G2|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|count24:G2|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|count60:G3|
|count60:G3|lpm_add_sub:115|
|count60:G3|lpm_add_sub:115|addcore:adder|
|count60:G3|lpm_add_sub:115|altshift:result_ext_latency_ffs|
|count60:G3|lpm_add_sub:115|altshift:carry_ext_latency_ffs|
|count60:G3|lpm_add_sub:115|altshift:oflow_ext_latency_ffs|
|count60:G3|lpm_add_sub:144|
|count60:G3|lpm_add_sub:144|addcore:adder|
|count60:G3|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|count60:G3|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|count60:G3|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|count60:G4|
|count60:G4|lpm_add_sub:115|
|count60:G4|lpm_add_sub:115|addcore:adder|
|count60:G4|lpm_add_sub:115|altshift:result_ext_latency_ffs|
|count60:G4|lpm_add_sub:115|altshift:carry_ext_latency_ffs|
|count60:G4|lpm_add_sub:115|altshift:oflow_ext_latency_ffs|
|count60:G4|lpm_add_sub:144|
|count60:G4|lpm_add_sub:144|addcore:adder|
|count60:G4|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|count60:G4|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|count60:G4|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|decode4_7:G5|
|decode4_7:G6|
Device-Specific Information: g:\top1\clock.rpt
clock
***** Logic for device 'clock' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S V S S S S S S c S S S S S V S S S S S S S S S S S S
E E E E E E E C E E E E E E V o E E E E E C E E V E E E E r E E E V E E E
R R R R R R R C R R R R R R C u R R R R R C R R C R R R R e R R R C R R R
V V V V V V V I V V V V V V C t V V V V G v V I G G G G V V C V V V V s V G V V h h h C h h h h e V V V
E E E E E E E N E E E E E E I 2 E E E E N c E N N N N N E E I E E E E e E N E E h h h I h h h h n E E E
D D D D D D D T D D D D D D O 4 D D D D D c D T D D D D D D O D D D D t D D D D 6 5 4 O 3 2 1 0 5 D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | mh0
RESERVED | 10 147 | mh1
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | mh2
RESERVED | 14 143 | mh3
RESERVED | 15 142 | ml0
RESERVED | 16 141 | ml1
RESERVED | 17 140 | ml2
RESERVED | 18 139 | ml3
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | sh0
VCCIO | 22 135 | sh1
GND | 23 134 | sh2
RESERVED | 24 133 | sh3
hl0 | 25 132 | sl0
hl1 | 26 131 | sl1
hl2 | 27 EP1K30QC208-3 130 | VCCINT
hl3 | 28 129 | GND
hl4 | 29 128 | sl2
hl5 | 30 127 | sl3
hl6 | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
en4 | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R m a c c V R R R G V G G G G G R V R R R R R R V R R e e e e V R R R R R R
E E E E E E N E E E E E E C E o d l l C E E E N C N N N N N E C E E E E E E C E E n n n n C E E E E E E
S S S S S S D S S S S S S C S d j k k C S S S D C D D D D D S C S S S S S S C S S 0 1 2 3 C S S S S S S
E E E E E E E E E E E E I E e u 1 2 I E E E I E I E E E E E E I E E I E E E E E E
R R R R R R R R R R R R O R s H H N R R R N R O R R R R R R N R R O R R R R R R
V V V V V V V V V V V V V t Z Z T V V V T V V V V V V V T V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: g:\top1\clock.rpt
clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B1 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
B2 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
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