mode_adjust.rpt

1．6个数码管静态显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、显示译码模块、顶层模块。要求使用实验箱右下角的6个

-- Node name is 'en4' 
-- Equation name is 'en4', type is output 
en4      =  _LC5_A13;

-- Node name is 'en5' 
-- Equation name is 'en5', type is output 
en5      =  _LC7_A13;

-- Node name is 'hin' 
-- Equation name is 'hin', type is output 
hin      =  _LC2_A14;

-- Node name is 'min' 
-- Equation name is 'min', type is output 
min      =  _LC4_A14;

-- Node name is ':537' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = LCELL( _EQ003);
  _EQ003 = !c_state0 &  c_state1;

-- Node name is ':545' 
-- Equation name is '_LC3_A14', type is buried 
!_LC3_A14 = _LC3_A14~NOT;
_LC3_A14~NOT = LCELL( _EQ004);
  _EQ004 =  c_state1
         # !c_state0;

-- Node name is ':580' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ005);
  _EQ005 =  adjust &  c_state0 & !c_state1
         #  clk1HZ & !c_state0 & !c_state1;

-- Node name is ':592' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ006);
  _EQ006 =  clk1HZ & !c_state0 & !c_state1
         #  adjust & !c_state0 &  c_state1;

-- Node name is ':604' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ007);
  _EQ007 =  clk1HZ & !c_state0 & !c_state1
         #  adjust &  c_state0 &  c_state1;

-- Node name is '~606~1' 
-- Equation name is '~606~1', location is LC2_A13, type is buried.
-- synthesized logic cell 
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ008);
  _EQ008 = !c_state0
         # !c_state1;

-- Node name is ':725' 
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = LCELL( _EQ009);
  _EQ009 =  _LC2_A6 &  reset
         #  _LC1_A6 & !reset;

-- Node name is ':731' 
-- Equation name is '_LC8_A6', type is buried 
_LC8_A6  = LCELL( _EQ010);
  _EQ010 =  _LC8_A6 &  reset
         #  _LC1_A13 & !reset;

-- Node name is ':737' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ011);
  _EQ011 =  _LC6_A13 &  reset
         #  _LC4_A13 & !reset;

-- Node name is ':743' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ012);
  _EQ012 =  _LC3_A13 &  reset
         # !_LC2_A13 & !reset
         #  clk2HZ & !reset;

-- Node name is ':749' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ013);
  _EQ013 = !_LC2_A13 & !reset
         #  clk2HZ & !reset
         #  _LC8_A13 &  reset;

-- Node name is ':755' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = LCELL( _EQ014);
  _EQ014 =  _LC6_A14 &  reset
         #  clk2HZ & !reset
         # !_LC8_A14 & !reset;

-- Node name is ':761' 
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = LCELL( _EQ015);
  _EQ015 =  clk2HZ & !reset
         # !_LC8_A14 & !reset
         #  _LC1_A14 &  reset;

-- Node name is ':767' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ016);
  _EQ016 =  _LC5_A13 &  reset
         #  clk2HZ & !reset
         # !_LC3_A14 & !reset;

-- Node name is ':773' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ017);
  _EQ017 =  clk2HZ & !reset
         # !_LC3_A14 & !reset
         #  _LC7_A13 &  reset;

-- Node name is ':779' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ018);
  _EQ018 =  _LC2_A14 &  reset
         #  c_state0 & !c_state1 & !reset
         #  c_state0 &  _LC2_A14;

-- Node name is ':785' 
-- Equation name is '_LC4_A14', type is buried 
_LC4_A14 = LCELL( _EQ019);
  _EQ019 =  _LC4_A14 &  reset
         #  c_state1 &  _LC4_A14
         # !c_state0 &  c_state1 & !reset;



Project Information                       e:\vhdl\61\hardware2\mode_adjust.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,730K