📄 mode_adjust.rpt
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mode_adjust
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
184 - - - -- INPUT ^ 0 0 0 3 adjust
182 - - - -- INPUT ^ 0 0 0 3 clk1HZ
80 - - - -- INPUT ^ 0 0 0 6 clk2HZ
79 - - - -- INPUT G ^ 0 0 0 0 mode
78 - - - -- INPUT ^ 0 0 0 13 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\vhdl\61\hardware2\mode_adjust.rpt
mode_adjust
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- OUTPUT 0 1 0 0 clkh
147 - - A -- OUTPUT 0 1 0 0 clkm
173 - - - 13 OUTPUT 0 1 0 0 clks
149 - - A -- OUTPUT 0 1 0 0 en0
87 - - - 14 OUTPUT 0 1 0 0 en1
148 - - A -- OUTPUT 0 1 0 0 en2
7 - - A -- OUTPUT 0 1 0 0 en3
10 - - A -- OUTPUT 0 1 0 0 en4
11 - - A -- OUTPUT 0 1 0 0 en5
174 - - - 14 OUTPUT 0 1 0 0 hin
9 - - A -- OUTPUT 0 1 0 0 min
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\vhdl\61\hardware2\mode_adjust.rpt
mode_adjust
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 14 DFFE + 1 1 0 9 c_state1 (:19)
- 5 - A 14 DFFE + 1 2 0 9 c_state0 (:20)
- 8 - A 14 AND2 0 2 0 3 :537
- 3 - A 14 OR2 ! 0 2 0 2 :545
- 1 - A 06 OR2 2 2 0 1 :580
- 1 - A 13 OR2 2 2 0 1 :592
- 4 - A 13 OR2 2 2 0 1 :604
- 2 - A 13 OR2 s ! 0 2 0 2 ~606~1
- 2 - A 06 OR2 1 1 1 0 :725
- 8 - A 06 OR2 1 1 1 0 :731
- 6 - A 13 OR2 1 1 1 0 :737
- 3 - A 13 OR2 2 1 1 0 :743
- 8 - A 13 OR2 2 1 1 0 :749
- 6 - A 14 OR2 2 1 1 0 :755
- 1 - A 14 OR2 2 1 1 0 :761
- 5 - A 13 OR2 2 1 1 0 :767
- 7 - A 13 OR2 2 1 1 0 :773
- 2 - A 14 OR2 1 2 1 0 :779
- 4 - A 14 OR2 1 2 1 0 :785
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\vhdl\61\hardware2\mode_adjust.rpt
mode_adjust
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/144( 3%) 7/ 72( 9%) 0/ 72( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\vhdl\61\hardware2\mode_adjust.rpt
mode_adjust
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 2 mode
Device-Specific Information: e:\vhdl\61\hardware2\mode_adjust.rpt
mode_adjust
** EQUATIONS **
adjust : INPUT;
clk1HZ : INPUT;
clk2HZ : INPUT;
mode : INPUT;
reset : INPUT;
-- Node name is 'clkh'
-- Equation name is 'clkh', type is output
clkh = _LC2_A6;
-- Node name is 'clkm'
-- Equation name is 'clkm', type is output
clkm = _LC8_A6;
-- Node name is 'clks'
-- Equation name is 'clks', type is output
clks = _LC6_A13;
-- Node name is ':20' = 'c_state0'
-- Equation name is 'c_state0', location is LC5_A14, type is buried.
c_state0 = DFFE( _EQ001, GLOBAL( mode), VCC, VCC, VCC);
_EQ001 = !c_state0 & !c_state1 & !reset
# _LC8_A14 & !reset;
-- Node name is ':19' = 'c_state1'
-- Equation name is 'c_state1', location is LC7_A14, type is buried.
c_state1 = DFFE( _EQ002, GLOBAL( mode), VCC, VCC, VCC);
_EQ002 = c_state0 & !c_state1 & !reset
# !c_state0 & c_state1 & !reset;
-- Node name is 'en0'
-- Equation name is 'en0', type is output
en0 = _LC3_A13;
-- Node name is 'en1'
-- Equation name is 'en1', type is output
en1 = _LC8_A13;
-- Node name is 'en2'
-- Equation name is 'en2', type is output
en2 = _LC6_A14;
-- Node name is 'en3'
-- Equation name is 'en3', type is output
en3 = _LC1_A14;
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