count60.rpt

1．6个数码管静态显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、显示译码模块、顶层模块。要求使用实验箱右下角的6个

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:          c:\maxplus2\shiyan\hardware2\count60.rpt
count60

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC25 cout
        | +--------------- LC22 hh0
        | | +------------- LC21 hh1
        | | | +----------- LC19 hh2
        | | | | +--------- LC18 hh3
        | | | | | +------- LC24 hl0
        | | | | | | +----- LC17 hl1
        | | | | | | | +--- LC20 hl2
        | | | | | | | | +- LC23 hl3
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> * * * * * - - - - | - * | <-- hh0
LC21 -> * - * * * - - - - | - * | <-- hh1
LC19 -> * - * * * - - - - | - * | <-- hh2
LC18 -> * - * * * - - - - | - * | <-- hh3
LC24 -> * * * * * * * * * | - * | <-- hl0
LC17 -> * * * * * - * * * | - * | <-- hl1
LC20 -> * * * * * - * * * | - * | <-- hl2
LC23 -> * * * * * - * - * | - * | <-- hl3

Pin
43   -> - - - - - - - - - | - - | <-- clk
4    -> - * * * * * * * * | - * | <-- en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:          c:\maxplus2\shiyan\hardware2\count60.rpt
count60

** EQUATIONS **

clk      : INPUT;
en       : INPUT;

-- Node name is 'cout' 
-- Equation name is 'cout', location is LC025, type is output.
 cout    = LCELL( _EQ001 $  GND);
  _EQ001 =  hh0 & !hh1 &  hh2 & !hh3 &  hl0 & !hl1 & !hl2 &  hl3;

-- Node name is 'hh0' = 'yh0' 
-- Equation name is 'hh0', location is LC022, type is output.
 hh0     = TFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  en &  hl0 & !hl1 & !hl2 &  hl3;

-- Node name is 'hh1' = 'yh1' 
-- Equation name is 'hh1', location is LC021, type is output.
 hh1     = TFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  en &  hh0 & !hh1 &  hh3 &  hl0 & !hl1 & !hl2 &  hl3
         #  en &  hh0 & !hh1 & !hh2 &  hl0 & !hl1 & !hl2 &  hl3
         #  en &  hh0 &  hh1 &  hl0 & !hl1 & !hl2 &  hl3;

-- Node name is 'hh2' = 'yh2' 
-- Equation name is 'hh2', location is LC019, type is output.
 hh2     = TFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  en &  hh0 & !hh1 &  hh2 & !hh3 &  hl0 & !hl1 & !hl2 &  hl3
         #  en &  hh0 &  hh1 &  hl0 & !hl1 & !hl2 &  hl3;

-- Node name is 'hh3' = 'yh3' 
-- Equation name is 'hh3', location is LC018, type is output.
 hh3     = TFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  en &  hh0 &  hh1 &  hh2 &  hl0 & !hl1 & !hl2 &  hl3;

-- Node name is 'hl0' = 'yl0' 
-- Equation name is 'hl0', location is LC024, type is output.
 hl0     = TFFE( en, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is 'hl1' = 'yl1' 
-- Equation name is 'hl1', location is LC017, type is output.
 hl1     = TFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  en &  hl0 & !hl1 &  hl2
         #  en &  hl0 & !hl1 & !hl3
         #  en &  hl0 &  hl1;

-- Node name is 'hl2' = 'yl2' 
-- Equation name is 'hl2', location is LC020, type is output.
 hl2     = TFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  en &  hl0 &  hl1;

-- Node name is 'hl3' = 'yl3' 
-- Equation name is 'hl3', location is LC023, type is output.
 hl3     = TFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  en &  hl0 & !hl1 & !hl2 &  hl3
         #  en &  hl0 &  hl1 &  hl2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                   c:\maxplus2\shiyan\hardware2\count60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,222K