mode_adjust.vhd

1．6个数码管静态显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、显示译码模块、顶层模块。要求使用实验箱右下角的6个

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mode_adjust IS
PORT (reset,mode,adjust,clk1HZ,clk2HZ:IN STD_LOGIC;
      clkh,clkm,clks,hin,min:OUT STD_LOGIC;
      en :OUT STD_LOGIC_VECTOR(0 TO 5) );
END mode_adjust;

ARCHITECTURE arc OF mode_adjust IS
TYPE MYSTATE IS(S0,S1,S2,S3);
SIGNAL c_state,next_state:MYSTATE;
BEGIN
PROCESS(reset,c_state)
BEGIN
IF reset='1' THEN
next_state<=S0;
ELSE
CASE c_state IS
WHEN S0=>next_state<=S1;
     clkh<=clk1HZ;
     clkm<=clk1HZ;
     clks<=clk1HZ;
     en<="111111";
     hin<='0';
     min<='0';
WHEN S1=>next_state<=S2;
     clkh<=adjust;
     en(5)<=clk2HZ;
     en(4)<=clk2HZ;
     en(3 DOWNTO 0)<="1111";
     clkm<='0';
     clks<='0';
     hin<='1';
     min<='0';
WHEN S2=>next_state<=S3;
     clkh<='0';
     clkm<=adjust;
     en(3)<=clk2HZ;
     en(2)<=clk2HZ;
     en(5 DOWNTO 4)<="11";
     en(1 DOWNTO 0)<="11";
     clks<='0';
     hin<='0';
     min<='1';
WHEN S3=>next_state<=S0;
     clkh<='0';
     clkm<='0';
     clks<=adjust;
     en(1)<=clk2HZ;
     en(0)<=clk2HZ;
     en(5 DOWNTO 2)<="1111";

END CASE;
END IF;
END PROCESS;

PROCESS(mode)
BEGIN
IF(mode'EVENT AND mode='1') THEN
c_state<=next_state;
END IF;
END PROCESS;
END arc;