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-- Node name is '|COUNT24:34|:19' = '|COUNT24:34|hq1'
-- Equation name is '_LC4_D4', type is buried
_LC4_D4 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = !_LC1_D4 & _LC4_D4
# !en & _LC4_D4
# en & _LC8_D4;
-- Node name is '|COUNT24:34|:18' = '|COUNT24:34|hq2'
-- Equation name is '_LC2_F6', type is buried
_LC2_F6 = DFFE( _LC2_F6, clk, VCC, VCC, VCC);
-- Node name is '|COUNT24:34|:17' = '|COUNT24:34|hq3'
-- Equation name is '_LC4_F6', type is buried
_LC4_F6 = DFFE( _LC4_F6, clk, VCC, VCC, VCC);
-- Node name is '|COUNT24:34|LPM_ADD_SUB:178|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D9', type is buried
_LC2_D9 = LCELL( _EQ004);
_EQ004 = _LC1_D9 & _LC3_D9;
-- Node name is '|COUNT24:34|LPM_ADD_SUB:178|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_D9', type is buried
_LC4_D9 = LCELL( _EQ005);
_EQ005 = _LC1_D9 & _LC3_D9 & _LC8_D9;
-- Node name is '|COUNT24:34|:16' = '|COUNT24:34|lq0'
-- Equation name is '_LC3_D9', type is buried
_LC3_D9 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = !en & _LC3_D9
# en & !_LC3_D9;
-- Node name is '|COUNT24:34|:15' = '|COUNT24:34|lq1'
-- Equation name is '_LC1_D9', type is buried
_LC1_D9 = DFFE( _EQ007, clk, VCC, VCC, VCC);
_EQ007 = _LC1_D9 & _LC3_D4 & !_LC3_D9
# !_LC1_D9 & _LC3_D4 & _LC3_D9
# !en & _LC1_D9;
-- Node name is '|COUNT24:34|:14' = '|COUNT24:34|lq2'
-- Equation name is '_LC8_D9', type is buried
_LC8_D9 = DFFE( _EQ008, clk, VCC, VCC, VCC);
_EQ008 = !_LC2_D9 & _LC3_D4 & _LC8_D9
# _LC2_D9 & _LC3_D4 & !_LC8_D9
# !en & _LC8_D9;
-- Node name is '|COUNT24:34|:13' = '|COUNT24:34|lq3'
-- Equation name is '_LC6_D9', type is buried
_LC6_D9 = DFFE( _EQ009, clk, VCC, VCC, VCC);
_EQ009 = _LC3_D4 & !_LC4_D9 & _LC6_D9
# _LC3_D4 & _LC4_D9 & !_LC6_D9
# !en & _LC6_D9;
-- Node name is '|COUNT24:34|:3'
-- Equation name is '_LC6_D4', type is buried
_LC6_D4 = DFFE( _EQ010, clk, VCC, VCC, VCC);
_EQ010 = en & _LC1_D4
# !en & _LC6_D4
# _LC6_D4 & _LC7_D4;
-- Node name is '|COUNT24:34|:98'
-- Equation name is '_LC7_D4', type is buried
_LC7_D4 = LCELL( _EQ011);
_EQ011 = _LC2_D4 & !_LC2_F6 & !_LC4_D4 & !_LC4_F6;
-- Node name is '|COUNT24:34|:117'
-- Equation name is '_LC1_D4', type is buried
_LC1_D4 = LCELL( _EQ012);
_EQ012 = _LC1_F6 & _LC7_D34;
-- Node name is '|COUNT24:34|~303~1'
-- Equation name is '_LC3_D4', type is buried
-- synthesized logic cell
_LC3_D4 = LCELL( _EQ013);
_EQ013 = en & !_LC7_D4 & !_LC7_D34
# en & !_LC1_F6 & !_LC7_D4;
-- Node name is '|SEGMEN4TO7:40|:384'
-- Equation name is '_LC1_F6', type is buried
!_LC1_F6 = _LC1_F6~NOT;
_LC1_F6~NOT = LCELL( _EQ014);
_EQ014 = _LC2_F6
# _LC5_D4
# _LC4_F6
# !_LC4_D4;
-- Node name is '|SEGMEN4TO7:40|:396'
-- Equation name is '_LC3_F6', type is buried
_LC3_F6 = LCELL( _EQ015);
_EQ015 = !_LC2_F6 & !_LC4_D4 & !_LC4_F6 & _LC5_D4;
-- Node name is '|SEGMEN4TO7:40|:408'
-- Equation name is '_LC5_F6', type is buried
!_LC5_F6 = _LC5_F6~NOT;
_LC5_F6~NOT = LCELL( _EQ016);
_EQ016 = _LC2_F6
# _LC5_D4
# _LC4_F6
# _LC4_D4;
-- Node name is '|SEGMEN4TO7:40|:413'
-- Equation name is '_LC4_F3', type is buried
_LC4_F3 = LCELL( _EQ017);
_EQ017 = _LC2_F6 & !_LC4_D4 & !_LC4_F6 & !_LC5_D4
# !_LC2_F6 & !_LC4_D4 & !_LC4_F6 & _LC5_D4;
-- Node name is '|SEGMEN4TO7:40|:449'
-- Equation name is '_LC7_F6', type is buried
_LC7_F6 = LCELL( _EQ018);
_EQ018 = _LC2_F6 & !_LC4_D4 & !_LC4_F6 & _LC5_D4
# _LC2_F6 & _LC4_D4 & !_LC4_F6 & !_LC5_D4;
-- Node name is '|SEGMEN4TO7:40|~521~1'
-- Equation name is '_LC8_F6', type is buried
-- synthesized logic cell
_LC8_F6 = LCELL( _EQ019);
_EQ019 = _LC2_F6 & !_LC4_D4 & !_LC4_F6 & !_LC5_D4
# !_LC2_F6 & _LC4_D4 & _LC4_F6 & !_LC5_D4
# _LC2_F6 & _LC4_D4 & !_LC4_F6 & _LC5_D4;
-- Node name is '|SEGMEN4TO7:40|:521'
-- Equation name is '_LC6_F6', type is buried
_LC6_F6 = LCELL( _EQ020);
_EQ020 = _LC3_F6 & !_LC5_F6
# !_LC5_F6 & _LC8_F6;
-- Node name is '|SEGMEN4TO7:40|~557~1'
-- Equation name is '_LC2_F7', type is buried
-- synthesized logic cell
_LC2_F7 = LCELL( _EQ021);
_EQ021 = !_LC2_F6 & !_LC4_D4 & _LC4_F6 & _LC5_D4
# _LC4_D4 & !_LC4_F6 & _LC5_D4
# _LC2_F6 & !_LC4_D4 & !_LC4_F6;
-- Node name is '|SEGMEN4TO7:40|:557'
-- Equation name is '_LC1_F7', type is buried
_LC1_F7 = LCELL( _EQ022);
_EQ022 = !_LC1_F6 & _LC2_F7 & !_LC5_F6
# _LC3_F6 & !_LC5_F6;
-- Node name is '|SEGMEN4TO7:40|:593'
-- Equation name is '_LC4_F7', type is buried
_LC4_F7 = LCELL( _EQ023);
_EQ023 = _LC4_D4 & !_LC4_F6 & _LC5_D4
# !_LC2_F6 & _LC4_D4 & !_LC4_F6
# !_LC2_F6 & !_LC4_F6 & _LC5_D4;
-- Node name is '|SEGMEN4TO7:40|:627'
-- Equation name is '_LC4_F10', type is buried
_LC4_F10 = LCELL( _EQ024);
_EQ024 = !_LC2_F6 & !_LC4_D4 & !_LC4_F6
# _LC2_F6 & _LC4_D4 & !_LC4_F6 & _LC5_D4;
-- Node name is '|SEGMEN4TO7:41|:300'
-- Equation name is '_LC2_D4', type is buried
_LC2_D4 = LCELL( _EQ025);
_EQ025 = !_LC1_D9 & _LC3_D9 & _LC6_D9 & !_LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:372'
-- Equation name is '_LC7_D34', type is buried
_LC7_D34 = LCELL( _EQ026);
_EQ026 = _LC1_D9 & _LC3_D9 & !_LC6_D9 & !_LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:384'
-- Equation name is '_LC2_D34', type is buried
_LC2_D34 = LCELL( _EQ027);
_EQ027 = _LC1_D9 & !_LC3_D9 & !_LC6_D9 & !_LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:399'
-- Equation name is '_LC5_D34', type is buried
!_LC5_D34 = _LC5_D34~NOT;
_LC5_D34~NOT = LCELL( _EQ028);
_EQ028 = _LC1_D9
# _LC6_D9
# _LC3_D9 & _LC8_D9
# !_LC3_D9 & !_LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:413'
-- Equation name is '_LC4_D34', type is buried
_LC4_D34 = LCELL( _EQ029);
_EQ029 = !_LC1_D9 & _LC3_D9 & !_LC6_D9 & !_LC8_D9
# !_LC1_D9 & !_LC3_D9 & !_LC6_D9 & _LC8_D9;
-- Node name is '|SEGMEN4TO7:41|~449~1'
-- Equation name is '_LC8_D34', type is buried
-- synthesized logic cell
_LC8_D34 = LCELL( _EQ030);
_EQ030 = _LC1_D9 & !_LC3_D9 & !_LC6_D9 & _LC8_D9
# !_LC1_D9 & _LC3_D9 & !_LC6_D9 & _LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:449'
-- Equation name is '_LC1_D34', type is buried
_LC1_D34 = LCELL( _EQ031);
_EQ031 = !_LC2_D34 & !_LC5_D34 & !_LC7_D34 & _LC8_D34;
-- Node name is '|SEGMEN4TO7:41|:521'
-- Equation name is '_LC3_D34', type is buried
_LC3_D34 = LCELL( _EQ032);
_EQ032 = !_LC1_D9 & _LC3_D9 & !_LC6_D9 & !_LC8_D9
# !_LC1_D9 & !_LC3_D9 & !_LC6_D9 & _LC8_D9
# _LC1_D9 & !_LC3_D9 & _LC6_D9 & !_LC8_D9
# _LC1_D9 & _LC3_D9 & !_LC6_D9 & _LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:557'
-- Equation name is '_LC5_D9', type is buried
_LC5_D9 = LCELL( _EQ033);
_EQ033 = !_LC1_D9 & _LC3_D9 & !_LC8_D9
# _LC3_D9 & !_LC6_D9
# !_LC1_D9 & !_LC6_D9 & _LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:593'
-- Equation name is '_LC6_D34', type is buried
_LC6_D34 = LCELL( _EQ034);
_EQ034 = _LC3_D9 & !_LC6_D9 & !_LC8_D9
# _LC1_D9 & _LC3_D9 & !_LC6_D9
# _LC1_D9 & !_LC6_D9 & !_LC8_D9;
-- Node name is '|SEGMEN4TO7:41|:627'
-- Equation name is '_LC7_D9', type is buried
_LC7_D9 = LCELL( _EQ035);
_EQ035 = _LC1_D9 & _LC3_D9 & !_LC6_D9 & _LC8_D9
# !_LC1_D9 & !_LC6_D9 & !_LC8_D9;
Project Information e:\top\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,975K
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