top.rpt
来自「用硬件描述语言(或混合原理图)设计模24计数器模块、4-7显示译码模块、顶层模块」· RPT 代码 · 共 949 行 · 第 1/3 页
RPT
949 行
Device-Specific Information: e:\top\top.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
24 - - C -- OUTPUT 0 1 0 0 cout
94 - - - 09 OUTPUT 0 0 0 0 DS1B
95 - - - 09 OUTPUT 0 0 0 0 DS2B
37 - - E -- OUTPUT 0 0 0 0 DS7C_en
160 - - - 04 OUTPUT 0 0 0 0 DS8C_en
161 - - - 04 OUTPUT 0 1 0 0 ha
162 - - - 05 OUTPUT 0 1 0 0 hb
163 - - - 06 OUTPUT 0 1 0 0 hc
164 - - - 06 OUTPUT 0 1 0 0 hd
166 - - - 07 OUTPUT 0 1 0 0 he
167 - - - 08 OUTPUT 0 1 0 0 hf
168 - - - 09 OUTPUT 0 1 0 0 hg
169 - - - 10 OUTPUT 0 0 0 0 hh
133 - - C -- OUTPUT 0 1 0 0 H0
134 - - C -- OUTPUT 0 1 0 0 H1
135 - - C -- OUTPUT 0 1 0 0 H2
136 - - C -- OUTPUT 0 1 0 0 H3
25 - - D -- OUTPUT 0 1 0 0 la
26 - - D -- OUTPUT 0 1 0 0 lb
27 - - D -- OUTPUT 0 1 0 0 lc
28 - - D -- OUTPUT 0 1 0 0 ld
29 - - D -- OUTPUT 0 1 0 0 le
30 - - D -- OUTPUT 0 1 0 0 lf
31 - - D -- OUTPUT 0 1 0 0 lg
36 - - E -- OUTPUT 0 0 0 0 lh
127 - - D -- OUTPUT 0 1 0 0 L0
128 - - D -- OUTPUT 0 1 0 0 L1
131 - - C -- OUTPUT 0 1 0 0 L2
132 - - C -- OUTPUT 0 1 0 0 L3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\top\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 09 AND2 0 2 0 1 |COUNT24:34|LPM_ADD_SUB:178|addcore:adder|:55
- 4 - D 09 AND2 0 3 0 1 |COUNT24:34|LPM_ADD_SUB:178|addcore:adder|:59
- 6 - D 04 DFFE 2 2 1 0 |COUNT24:34|:3
- 6 - D 09 DFFE 2 2 1 10 |COUNT24:34|lq3 (|COUNT24:34|:13)
- 8 - D 09 DFFE 2 2 1 11 |COUNT24:34|lq2 (|COUNT24:34|:14)
- 1 - D 09 DFFE 2 2 1 12 |COUNT24:34|lq1 (|COUNT24:34|:15)
- 3 - D 09 DFFE 2 0 1 13 |COUNT24:34|lq0 (|COUNT24:34|:16)
- 4 - F 06 DFFE 1 0 1 10 |COUNT24:34|hq3 (|COUNT24:34|:17)
- 2 - F 06 DFFE 1 0 1 10 |COUNT24:34|hq2 (|COUNT24:34|:18)
- 4 - D 04 DFFE 2 2 1 10 |COUNT24:34|hq1 (|COUNT24:34|:19)
- 5 - D 04 DFFE 2 1 1 10 |COUNT24:34|hq0 (|COUNT24:34|:20)
- 7 - D 04 AND2 0 4 0 4 |COUNT24:34|:98
- 1 - D 04 AND2 0 2 0 2 |COUNT24:34|:117
- 3 - D 04 OR2 s 1 3 0 3 |COUNT24:34|~303~1
- 8 - D 04 AND2 s 0 2 0 1 en~1
- 1 - F 06 OR2 ! 0 4 1 3 |SEGMEN4TO7:40|:384
- 3 - F 06 AND2 0 4 0 2 |SEGMEN4TO7:40|:396
- 5 - F 06 OR2 ! 0 4 0 2 |SEGMEN4TO7:40|:408
- 4 - F 03 OR2 0 4 1 0 |SEGMEN4TO7:40|:413
- 7 - F 06 OR2 0 4 1 0 |SEGMEN4TO7:40|:449
- 8 - F 06 OR2 s 0 4 0 1 |SEGMEN4TO7:40|~521~1
- 6 - F 06 OR2 0 3 1 0 |SEGMEN4TO7:40|:521
- 2 - F 07 OR2 s 0 4 0 1 |SEGMEN4TO7:40|~557~1
- 1 - F 07 OR2 0 4 1 0 |SEGMEN4TO7:40|:557
- 4 - F 07 OR2 0 4 1 0 |SEGMEN4TO7:40|:593
- 4 - F 10 OR2 0 4 1 0 |SEGMEN4TO7:40|:627
- 2 - D 04 AND2 0 4 0 1 |SEGMEN4TO7:41|:300
- 7 - D 34 AND2 0 4 0 3 |SEGMEN4TO7:41|:372
- 2 - D 34 AND2 0 4 1 1 |SEGMEN4TO7:41|:384
- 5 - D 34 OR2 ! 0 4 0 1 |SEGMEN4TO7:41|:399
- 4 - D 34 OR2 0 4 1 0 |SEGMEN4TO7:41|:413
- 8 - D 34 OR2 s 0 4 0 1 |SEGMEN4TO7:41|~449~1
- 1 - D 34 AND2 0 4 1 0 |SEGMEN4TO7:41|:449
- 3 - D 34 OR2 0 4 1 0 |SEGMEN4TO7:41|:521
- 5 - D 09 OR2 0 4 1 0 |SEGMEN4TO7:41|:557
- 6 - D 34 OR2 0 4 1 0 |SEGMEN4TO7:41|:593
- 7 - D 09 OR2 0 4 1 0 |SEGMEN4TO7:41|:627
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\top\top.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/144( 0%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 13/144( 9%) 2/ 72( 2%) 5/ 72( 6%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
F: 3/144( 2%) 7/ 72( 9%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\top\top.rpt
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** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: e:\top\top.rpt
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** EQUATIONS **
clk : INPUT;
en : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC6_D4;
-- Node name is 'DS1B'
-- Equation name is 'DS1B', type is output
DS1B = VCC;
-- Node name is 'DS2B'
-- Equation name is 'DS2B', type is output
DS2B = VCC;
-- Node name is 'DS7C_en'
-- Equation name is 'DS7C_en', type is output
DS7C_en = VCC;
-- Node name is 'DS8C_en'
-- Equation name is 'DS8C_en', type is output
DS8C_en = VCC;
-- Node name is 'en~1'
-- Equation name is 'en~1', location is LC8_D4, type is buried.
-- synthesized logic cell
_LC8_D4 = LCELL( _EQ001);
_EQ001 = _LC5_D4 & _LC7_D4;
-- Node name is 'ha'
-- Equation name is 'ha', type is output
ha = _LC4_F3;
-- Node name is 'hb'
-- Equation name is 'hb', type is output
hb = _LC7_F6;
-- Node name is 'hc'
-- Equation name is 'hc', type is output
hc = _LC1_F6;
-- Node name is 'hd'
-- Equation name is 'hd', type is output
hd = _LC6_F6;
-- Node name is 'he'
-- Equation name is 'he', type is output
he = _LC1_F7;
-- Node name is 'hf'
-- Equation name is 'hf', type is output
hf = _LC4_F7;
-- Node name is 'hg'
-- Equation name is 'hg', type is output
hg = _LC4_F10;
-- Node name is 'hh'
-- Equation name is 'hh', type is output
hh = VCC;
-- Node name is 'H0'
-- Equation name is 'H0', type is output
H0 = _LC5_D4;
-- Node name is 'H1'
-- Equation name is 'H1', type is output
H1 = _LC4_D4;
-- Node name is 'H2'
-- Equation name is 'H2', type is output
H2 = _LC2_F6;
-- Node name is 'H3'
-- Equation name is 'H3', type is output
H3 = _LC4_F6;
-- Node name is 'la'
-- Equation name is 'la', type is output
la = _LC4_D34;
-- Node name is 'lb'
-- Equation name is 'lb', type is output
lb = _LC1_D34;
-- Node name is 'lc'
-- Equation name is 'lc', type is output
lc = _LC2_D34;
-- Node name is 'ld'
-- Equation name is 'ld', type is output
ld = _LC3_D34;
-- Node name is 'le'
-- Equation name is 'le', type is output
le = _LC5_D9;
-- Node name is 'lf'
-- Equation name is 'lf', type is output
lf = _LC6_D34;
-- Node name is 'lg'
-- Equation name is 'lg', type is output
lg = _LC7_D9;
-- Node name is 'lh'
-- Equation name is 'lh', type is output
lh = VCC;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = _LC3_D9;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC1_D9;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC8_D9;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC6_D9;
-- Node name is '|COUNT24:34|:20' = '|COUNT24:34|hq0'
-- Equation name is '_LC5_D4', type is buried
_LC5_D4 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = _LC5_D4 & !_LC7_D4
# en & !_LC5_D4 & _LC7_D4
# !en & _LC5_D4;
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