📄 top.rpt
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- 3 - D 02 OR2 s ! 0 2 0 1 |cout60:amin|~228~1
- 1 - D 02 OR2 s ! 0 2 0 3 |cout60:amin|~298~1
- 6 - D 02 OR2 0 4 0 2 |cout60:amin|:298
- 7 - D 02 OR2 0 4 0 1 |cout60:amin|:359
- 2 - D 02 OR2 s 0 3 0 3 |cout60:amin|~423~1
- 3 - D 01 AND2 s 1 2 0 2 |cout60:amin|~423~2
- 5 - D 17 AND2 0 2 0 2 |cout60:minc|LPM_ADD_SUB:160|addcore:adder|:55
- 5 - D 13 DFFE 0 3 0 1 |cout60:minc|:11
- 1 - D 13 DFFE 0 4 0 4 |cout60:minc|al3 (|cout60:minc|:21)
- 2 - D 13 DFFE 0 4 0 4 |cout60:minc|al2 (|cout60:minc|:22)
- 2 - D 17 DFFE 0 4 0 4 |cout60:minc|al1 (|cout60:minc|:23)
- 1 - D 17 DFFE 0 2 0 6 |cout60:minc|al0 (|cout60:minc|:24)
- 1 - D 14 DFFE 0 1 0 3 |cout60:minc|ah3 (|cout60:minc|:25)
- 2 - D 12 DFFE 0 3 0 5 |cout60:minc|ah2 (|cout60:minc|:26)
- 8 - D 12 DFFE 0 4 0 4 |cout60:minc|ah1 (|cout60:minc|:27)
- 5 - D 12 DFFE 0 4 0 7 |cout60:minc|ah0 (|cout60:minc|:28)
- 8 - D 14 AND2 s 0 4 0 2 |cout60:minc|~188~1
- 1 - D 12 AND2 0 4 0 3 |cout60:minc|:188
- 8 - D 13 OR2 0 4 0 1 |cout60:minc|:191
- 3 - D 12 AND2 s 0 2 0 3 |cout60:minc|~228~1
- 3 - D 05 OR2 s ! 0 2 0 3 |cout60:minc|~298~1
- 6 - D 12 OR2 ! 0 4 0 3 |cout60:minc|:298
- 7 - D 12 OR2 0 4 0 1 |cout60:minc|:359
- 7 - D 13 AND2 s 0 3 0 2 |cout60:minc|~423~1
- 4 - D 12 OR2 s 0 4 0 3 |cout60:minc|~429~1
- 7 - D 04 AND2 0 2 0 2 |cout60:secc|LPM_ADD_SUB:160|addcore:adder|:55
- 6 - D 13 DFFE 1 3 0 2 |cout60:secc|:11
- 4 - D 04 DFFE 0 4 0 3 |cout60:secc|al3 (|cout60:secc|:21)
- 3 - D 04 DFFE 0 4 0 3 |cout60:secc|al2 (|cout60:secc|:22)
- 5 - D 04 DFFE 0 4 0 3 |cout60:secc|al1 (|cout60:secc|:23)
- 4 - D 18 DFFE 1 2 0 5 |cout60:secc|al0 (|cout60:secc|:24)
- 2 - D 11 DFFE 0 1 0 2 |cout60:secc|ah3 (|cout60:secc|:25)
- 5 - D 08 DFFE 0 3 0 5 |cout60:secc|ah2 (|cout60:secc|:26)
- 4 - D 08 DFFE 0 4 0 4 |cout60:secc|ah1 (|cout60:secc|:27)
- 3 - D 08 DFFE 0 4 0 6 |cout60:secc|ah0 (|cout60:secc|:28)
- 1 - D 04 OR2 ! 0 4 0 3 |cout60:secc|:188
- 8 - D 04 OR2 0 4 0 1 |cout60:secc|:191
- 2 - D 04 OR2 s 0 4 0 2 |cout60:secc|~228~1
- 6 - D 08 OR2 s 0 3 0 3 |cout60:secc|~228~2
- 2 - D 08 OR2 s 0 2 0 1 |cout60:secc|~228~3
- 2 - D 18 OR2 s 0 2 0 3 |cout60:secc|~298~1
- 7 - D 08 OR2 ! 0 4 0 3 |cout60:secc|:298
- 8 - D 08 OR2 0 4 0 1 |cout60:secc|:359
- 6 - D 04 AND2 s 0 3 0 2 |cout60:secc|~423~1
- 1 - D 08 OR2 s 0 3 0 2 |cout60:secc|~429~1
- 1 - D 33 DFFE 2 4 0 8 |mode_adjust:control|c_state2 (|mode_adjust:control|:16)
- 8 - D 33 DFFE 2 3 0 7 |mode_adjust:control|c_state1 (|mode_adjust:control|:17)
- 2 - D 30 DFFE 2 3 0 6 |mode_adjust:control|c_state0 (|mode_adjust:control|:18)
- 5 - D 30 OR2 ! 0 3 0 6 |mode_adjust:control|:325
- 3 - D 30 OR2 ! 0 3 0 2 |mode_adjust:control|:328
- 6 - D 30 OR2 ! 0 3 0 6 |mode_adjust:control|:335
- 7 - D 30 OR2 ! 0 3 0 6 |mode_adjust:control|:345
- 1 - D 30 OR2 ! 0 3 0 7 |mode_adjust:control|:355
- 1 - D 34 OR2 1 3 0 1 |mode_adjust:control|:409
- 5 - D 34 OR2 1 2 0 8 |mode_adjust:control|:412
- 7 - D 33 OR2 2 2 0 1 |mode_adjust:control|:424
- 3 - D 33 OR2 1 3 0 9 |mode_adjust:control|:430
- 2 - D 33 AND2 1 1 0 1 |mode_adjust:control|:440
- 8 - D 34 AND2 1 1 0 2 |mode_adjust:control|:441
- 5 - D 33 OR2 0 4 0 9 |mode_adjust:control|:448
- 3 - D 34 AND2 1 1 0 1 |mode_adjust:control|:449
- 8 - D 30 AND2 1 3 0 8 |mode_adjust:control|:522
- 4 - D 33 AND2 s 0 3 0 2 |mode_adjust:control|~540~1
- 6 - D 33 AND2 1 2 0 8 |mode_adjust:control|:540
- 3 - D 20 AND2 0 3 0 4 |muxcmp:muxcomp|:147
- 6 - D 19 AND2 0 3 0 8 |muxcmp:muxcomp|:161
- 7 - D 19 AND2 0 4 0 8 |muxcmp:muxcomp|:175
- 4 - D 19 OR2 0 4 0 8 |muxcmp:muxcomp|:182
- 3 - D 11 OR2 0 3 0 1 |muxcmp:muxcomp|:291
- 4 - D 11 OR2 0 3 0 1 |muxcmp:muxcomp|:297
- 5 - D 11 OR2 0 3 0 1 |muxcmp:muxcomp|:303
- 6 - D 11 OR2 0 3 0 1 |muxcmp:muxcomp|:309
- 7 - D 11 OR2 0 3 0 1 |muxcmp:muxcomp|:315
- 8 - D 11 OR2 0 3 0 1 |muxcmp:muxcomp|:321
- 2 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:327
- 3 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:330
- 5 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:333
- 1 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:336
- 3 - D 03 OR2 0 3 0 1 |muxcmp:muxcomp|:339
- 4 - D 03 OR2 0 3 0 1 |muxcmp:muxcomp|:342
- 4 - D 17 OR2 0 3 0 1 |muxcmp:muxcomp|:348
- 6 - D 17 OR2 0 3 0 1 |muxcmp:muxcomp|:351
- 7 - D 17 OR2 0 3 0 1 |muxcmp:muxcomp|:354
- 8 - D 17 OR2 0 3 0 1 |muxcmp:muxcomp|:357
- 3 - D 17 OR2 0 3 0 1 |muxcmp:muxcomp|:360
- 3 - D 07 OR2 0 3 0 1 |muxcmp:muxcomp|:363
- 1 - D 18 OR2 0 3 0 1 |muxcmp:muxcomp|:369
- 3 - D 18 OR2 0 3 0 1 |muxcmp:muxcomp|:372
- 6 - D 18 OR2 0 3 0 1 |muxcmp:muxcomp|:375
- 7 - D 18 OR2 0 3 0 1 |muxcmp:muxcomp|:378
- 8 - D 18 OR2 0 3 0 1 |muxcmp:muxcomp|:381
- 5 - D 18 OR2 0 3 0 1 |muxcmp:muxcomp|:384
- 7 - D 20 OR2 ! 0 3 0 4 |muxcmp:muxcomp|:425
- 3 - D 19 AND2 0 3 0 4 |muxcmp:muxcomp|:439
- 3 - D 15 OR2 0 3 0 1 |muxcmp:muxcomp|:546
- 6 - D 15 OR2 0 3 0 1 |muxcmp:muxcomp|:552
- 7 - D 15 OR2 0 3 0 1 |muxcmp:muxcomp|:558
- 4 - D 15 OR2 0 4 0 1 |muxcmp:muxcomp|:570
- 6 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:582
- 7 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:585
- 4 - D 10 OR2 0 3 0 1 |muxcmp:muxcomp|:588
- 7 - D 03 OR2 0 4 0 1 |muxcmp:muxcomp|:594
- 5 - D 07 OR2 0 3 0 1 |muxcmp:muxcomp|:603
- 6 - D 07 OR2 0 3 0 1 |muxcmp:muxcomp|:606
- 7 - D 07 OR2 0 3 0 1 |muxcmp:muxcomp|:609
- 8 - D 07 OR2 0 3 0 1 |muxcmp:muxcomp|:612
- 7 - D 16 OR2 0 3 0 1 |muxcmp:muxcomp|:624
- 3 - D 16 OR2 0 3 0 1 |muxcmp:muxcomp|:627
- 4 - D 29 OR2 0 3 0 1 |muxcmp:muxcomp|:630
- 8 - D 16 OR2 0 3 0 1 |muxcmp:muxcomp|:633
- 5 - D 16 AND2 ! 0 1 0 4 |muxcmp:muxcomp|:676
- 1 - D 11 OR2 0 3 0 9 |muxcmp:muxcomp|:677
- 5 - D 03 OR2 0 3 0 9 |muxcmp:muxcomp|:683
- 1 - D 07 OR2 0 4 0 9 |muxcmp:muxcomp|:689
- 4 - D 16 OR2 0 4 0 9 |muxcmp:muxcomp|:695
- 2 - D 14 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~1
- 4 - D 09 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~2
- 3 - D 14 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~3
- 5 - D 14 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~4
- 6 - D 14 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~5
- 7 - D 14 AND2 s 0 4 0 1 |muxcmp:muxcomp|~818~6
- 8 - D 06 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~7
- 8 - D 15 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~8
- 5 - D 06 AND2 s 1 2 0 1 |muxcmp:muxcomp|~818~9
- 6 - D 03 OR2 s 0 4 0 1 |muxcmp:muxcomp|~818~10
- 4 - D 14 AND2 0 4 1 0 |muxcmp:muxcomp|:818
- 2 - D 20 DFFE 1 3 0 11 |scan:scaner|c_state2 (|scan:scaner|:5)
- 2 - D 19 DFFE 1 2 0 11 |scan:scaner|c_state1 (|scan:scaner|:6)
- 1 - D 20 DFFE 1 1 0 11 |scan:scaner|c_state0 (|scan:scaner|:7)
- 1 - D 19 AND2 0 3 0 6 |scan:scaner|:142
- 8 - D 19 AND2 0 3 0 5 |scan:scaner|:162
- 4 - D 20 AND2 s 0 2 0 1 |scan:scaner|~172~1
- 5 - D 19 OR2 ! 0 4 1 4 |scan:scaner|:231
- 5 - D 20 OR2 s 0 4 0 2 |scan:scaner|~249~1
- 6 - D 20 OR2 ! 0 2 1 2 |scan:scaner|:249
- 1 - D 21 OR2 ! 0 3 1 2 |scan:scaner|:267
- 8 - D 10 OR2 0 4 1 0 |seg4_7:deco|:371
- 2 - A 12 OR2 0 4 1 0 |seg4_7:deco|:404
- 1 - A 12 OR2 0 4 1 0 |seg4_7:deco|:437
- 4 - A 14 OR2 0 4 1 0 |seg4_7:deco|:470
- 5 - A 14 OR2 0 4 1 0 |seg4_7:deco|:503
- 1 - A 14 OR2 0 4 1 0 |seg4_7:deco|:536
- 6 - D 16 OR2 0 4 1 0 |seg4_7:deco|:571
- 3 - D 13 OR2 ! 0 3 0 7 :116
- 4 - D 13 AND2 ! 0 2 0 9 :117
- 1 - D 24 AND2 ! 1 1 0 7 :118
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\alarm\top.rpt
top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 4/ 72( 5%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 73/144( 50%) 36/ 72( 50%) 9/ 72( 12%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\alarm\top.rpt
top
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 9 |mode_adjust:control|:430
LCELL 9 |mode_adjust:control|:448
LCELL 8 |mode_adjust:control|:412
LCELL 8 |mode_adjust:control|:522
LCELL 8 |mode_adjust:control|:540
INPUT 3 clks
INPUT 3 mode
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