📄 top.rpt
字号:
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R s V s s R G V G G G G G R V R f f f f f V f f R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E s C s s E N C N N N N N E C E o o o o o C o o E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S 0 C 1 2 S D C D D D D D S C S u u u u u C u u S S S S C S S S S S S
E E E E E E E E E E E E I E E E E I E I E I E t t t t t I t t E E E E I E E E E E E
R R R R R R R R R R R R O R R R R N R N R O R 0 1 2 3 4 N 5 6 R R R R O R R R R R R
V V V V V V V V V V V V V V V V T V T V V T V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\wxl\alarm\alarm\top.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
E1 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 14/22( 63%)
E2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 10/22( 45%)
E3 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
E4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
E5 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
E6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 15/22( 68%)
E7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 13/22( 59%)
E8 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 13/22( 59%)
E9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 11/22( 50%)
E10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
E11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
E12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
E14 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
E15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
E17 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
E18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 16/22( 72%)
E19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
E20 7/ 8( 87%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
E21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
E22 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 1/2 0/2 2/22( 9%)
E23 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
E30 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
E31 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
E36 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
F9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F12 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F13 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 18/141 ( 12%)
Total logic cells used: 193/1728 ( 11%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.19/4 ( 79%)
Total fan-in: 617/6912 ( 8%)
Total input pins required: 7
Total input I/O cell registers required: 0
Total output pins required: 11
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 193
Total flipflops required: 48
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 39/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 8 8 0 8 7 8 8 8 0 0 0 0 0 0 3 1 0 0 0 0 7 186/0
F: 0 0 0 0 0 0 0 0 1 0 0 2 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7/0
Total: 8 8 8 8 8 8 8 8 9 8 8 10 11 8 9 0 8 8 0 8 7 8 8 8 0 0 0 0 0 0 3 1 0 0 0 0 7 193/0
Device-Specific Information: e:\wxl\alarm\alarm\top.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
197 - - - 28 INPUT ^ 0 0 0 5 adjust
193 - - - 25 INPUT ^ 0 0 0 1 clka
192 - - - 24 INPUT ^ 0 0 0 3 clks
191 - - - 23 INPUT ^ 0 0 0 5 clk1
195 - - - 26 INPUT ^ 0 0 0 18 en
198 - - - 28 INPUT ^ 0 0 0 3 mode
196 - - - 27 INPUT ^ 0 0 0 3 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\wxl\alarm\alarm\top.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - E -- OUTPUT 0 1 0 0 aout
86 - - - 15 OUTPUT 0 1 0 0 fout0
87 - - - 14 OUTPUT 0 1 0 0 fout1
88 - - - 14 OUTPUT 0 1 0 0 fout2
89 - - - 13 OUTPUT 0 1 0 0 fout3
90 - - - 12 OUTPUT 0 1 0 0 fout4
92 - - - 11 OUTPUT 0 1 0 0 fout5
93 - - - 10 OUTPUT 0 1 0 0 fout6
71 - - - 21 OUTPUT 0 1 0 0 ss0
73 - - - 20 OUTPUT 0 1 0 0 ss1
74 - - - 20 OUTPUT 0 1 0 0 ss2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\wxl\alarm\alarm\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - E 36 AND2 0 2 0 3 |cnt24:ahour|LPM_ADD_SUB:200|addcore:adder|:55
- 3 - E 36 AND2 0 2 0 1 |cnt24:ahour|LPM_ADD_SUB:200|addcore:adder|:59
- 4 - E 09 DFFE 0 1 0 3 |cnt24:ahour|ah3 (|cnt24:ahour|:11)
- 3 - E 09 DFFE 0 1 0 3 |cnt24:ahour|ah2 (|cnt24:ahour|:12)
- 8 - E 21 DFFE 1 3 0 5 |cnt24:ahour|ah1 (|cnt24:ahour|:13)
- 5 - E 21 DFFE 1 2 0 5 |cnt24:ahour|ah0 (|cnt24:ahour|:14)
- 2 - E 36 DFFE 1 3 0 4 |cnt24:ahour|al3 (|cnt24:ahour|:15)
- 8 - E 36 DFFE 1 3 0 4 |cnt24:ahour|al2 (|cnt24:ahour|:16)
- 7 - E 36 DFFE 1 3 0 4 |cnt24:ahour|al1 (|cnt24:ahour|:17)
- 5 - E 36 DFFE 1 1 0 5 |cnt24:ahour|al0 (|cnt24:ahour|:18)
- 7 - E 21 OR2 ! 0 2 0 1 |cnt24:ahour|:101
- 1 - E 36 OR2 s ! 0 3 0 1 |cnt24:ahour|~120~1
- 2 - E 09 OR2 s ! 0 3 0 2 |cnt24:ahour|~120~2
- 1 - E 21 OR2 s ! 0 3 0 4 |cnt24:ahour|~120~3
- 3 - E 21 OR2 s 0 3 0 1 |cnt24:ahour|~139~1
- 4 - E 21 OR2 ! 0 3 0 2 |cnt24:ahour|:139
- 6 - E 21 OR2 0 4 0 1 |cnt24:ahour|:251
- 2 - E 21 AND2 s 1 2 0 3 |cnt24:ahour|~359~1
- 3 - E 14 AND2 0 2 0 3 |cnt24:hourc|LPM_ADD_SUB:200|addcore:adder|:55
- 6 - E 14 AND2 0 2 0 1 |cnt24:hourc|LPM_ADD_SUB:200|addcore:adder|:59
- 1 - E 08 DFFE 0 1 0 3 |cnt24:hourc|ah3 (|cnt24:hourc|:11)
- 2 - E 08 DFFE 0 1 0 3 |cnt24:hourc|ah2 (|cnt24:hourc|:12)
- 5 - E 12 DFFE 0 4 0 5 |cnt24:hourc|ah1 (|cnt24:hourc|:13)
- 8 - E 12 DFFE 0 3 0 5 |cnt24:hourc|ah0 (|cnt24:hourc|:14)
- 1 - E 14 DFFE 0 4 0 4 |cnt24:hourc|al3 (|cnt24:hourc|:15)
- 2 - E 14 DFFE 0 4 0 4 |cnt24:hourc|al2 (|cnt24:hourc|:16)
- 5 - E 14 DFFE 0 4 0 4 |cnt24:hourc|al1 (|cnt24:hourc|:17)
- 8 - E 14 DFFE 0 2 0 5 |cnt24:hourc|al0 (|cnt24:hourc|:18)
- 7 - E 12 OR2 ! 0 2 0 1 |cnt24:hourc|:101
- 1 - E 04 OR2 s ! 0 3 0 1 |cnt24:hourc|~120~1
- 8 - E 08 OR2 s ! 0 3 0 2 |cnt24:hourc|~120~2
- 2 - E 04 OR2 s ! 0 3 0 4 |cnt24:hourc|~120~3
- 2 - E 12 OR2 s 0 3 0 1 |cnt24:hourc|~139~1
- 4 - E 12 OR2 ! 0 3 0 2 |cnt24:hourc|:139
- 6 - E 12 OR2 0 4 0 1 |cnt24:hourc|:251
- 1 - E 12 AND2 s 0 3 0 3 |cnt24:hourc|~359~1
- 7 - E 15 AND2 0 2 0 2 |cout60:amin|LPM_ADD_SUB:160|addcore:adder|:55
- 1 - E 15 DFFE 1 3 0 4 |cout60:amin|al3 (|cout60:amin|:21)
- 3 - E 15 DFFE 1 3 0 4 |cout60:amin|al2 (|cout60:amin|:22)
- 4 - E 15 DFFE 1 3 0 4 |cout60:amin|al1 (|cout60:amin|:23)
- 8 - E 17 DFFE 1 1 0 6 |cout60:amin|al0 (|cout60:amin|:24)
- 1 - E 31 DFFE 0 1 0 3 |cout60:amin|ah3 (|cout60:amin|:25)
- 3 - E 03 DFFE 1 2 0 6 |cout60:amin|ah2 (|cout60:amin|:26)
- 6 - E 03 DFFE 1 3 0 6 |cout60:amin|ah1 (|cout60:amin|:27)
- 4 - E 03 DFFE 1 3 0 6 |cout60:amin|ah0 (|cout60:amin|:28)
- 2 - E 15 OR2 s ! 0 4 0 2 |cout60:amin|~188~1
- 5 - E 15 OR2 ! 0 4 0 2 |cout60:amin|:188
- 8 - E 15 OR2 0 4 0 1 |cout60:amin|:191
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