📄 scan.vhd
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY scan IS
PORT(clk:IN STD_LOGIC;
d:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END scan;
ARCHITECTURE arc OF scan IS
TYPE mystate IS (s0,s1,s2,s3,s4,s5);
SIGNAL c_state,n_state: mystate;
BEGIN
PROCESS(c_state)
BEGIN
CASE c_state IS
WHEN s0=>
n_state<=s1;
d<="000";
WHEN s1=>
n_state<=s2;
d<="001";
WHEN s2=>
n_state<=s3;
d<="100";
WHEN s3=>
n_state<=s4;
d<="101";
WHEN s4=>
n_state<=s5;
d<="110";
WHEN s5=>
n_state<=s0;
d<="111";
END CASE;
END PROCESS;
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1')THEN
c_state<=n_state;
END IF;
END PROCESS;
END arc;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -