📄 mode_adjust.rpt
字号:
mode_adjust
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC27 ahc
| +----------------------- LC29 amc
| | +--------------------- LC25 enh
| | | +------------------- LC28 enm
| | | | +----------------- LC26 ens
| | | | | +--------------- LC24 hcl
| | | | | | +------------- LC22 mcl
| | | | | | | +----------- LC20 modes0
| | | | | | | | +--------- LC19 modes1
| | | | | | | | | +------- LC17 modes2
| | | | | | | | | | +----- LC18 scl
| | | | | | | | | | | +--- LC21 c_state1
| | | | | | | | | | | | +- LC23 c_state0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * * * * * * * * * * * * * | - * | <-- modes2
LC21 -> * * * * * * * * * * * * * | - * | <-- c_state1
LC23 -> * * * * * * * * - * * * * | - * | <-- c_state0
Pin
4 -> * * - - - * * - - - * - - | - * | <-- adjust
5 -> - - - - - * * - - - * - - | - * | <-- clk1
43 -> - - - - - - - - - - - - - | - - | <-- mode
6 -> - - - - - - - - - * - * * | - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\taeyeon\alarm\mode_adjust.rpt
mode_adjust
** EQUATIONS **
adjust : INPUT;
clk1 : INPUT;
mode : INPUT;
reset : INPUT;
-- Node name is 'ahc'
-- Equation name is 'ahc', location is LC027, type is output.
ahc = LCELL( _EQ001 $ GND);
_EQ001 = adjust & !c_state0 & !c_state1 & modes2;
-- Node name is 'amc'
-- Equation name is 'amc', location is LC029, type is output.
amc = LCELL( _EQ002 $ modes2);
_EQ002 = !c_state0 & !c_state1 & modes2
# !adjust & modes2;
-- Node name is ':18' = 'c_state0'
-- Equation name is 'c_state0', location is LC023, type is buried.
c_state0 = TFFE(!_EQ003, GLOBAL( mode), !reset, VCC, VCC);
_EQ003 = !c_state0 & c_state1 & modes2;
-- Node name is ':17' = 'c_state1'
-- Equation name is 'c_state1', location is LC021, type is buried.
c_state1 = DFFE( _EQ004 $ !modes2, GLOBAL( mode), !reset, VCC, VCC);
_EQ004 = c_state0 & c_state1 & !modes2
# !c_state0 & !c_state1 & !modes2;
-- Node name is 'enh'
-- Equation name is 'enh', location is LC025, type is output.
enh = LCELL( _EQ005 $ GND);
_EQ005 = c_state0 & !c_state1 & !modes2;
-- Node name is 'enm'
-- Equation name is 'enm', location is LC028, type is output.
enm = LCELL( _EQ006 $ GND);
_EQ006 = !c_state0 & c_state1 & !modes2;
-- Node name is 'ens'
-- Equation name is 'ens', location is LC026, type is output.
ens = LCELL( _EQ007 $ GND);
_EQ007 = c_state0 & c_state1 & !modes2;
-- Node name is 'hcl'
-- Equation name is 'hcl', location is LC024, type is output.
hcl = LCELL( _EQ008 $ clk1);
_EQ008 = adjust & !clk1 & c_state0 & !c_state1 & !modes2
# !adjust & clk1 & c_state0 & !modes2
# clk1 & c_state1 & !modes2;
-- Node name is 'mcl'
-- Equation name is 'mcl', location is LC022, type is output.
mcl = LCELL( _EQ009 $ clk1);
_EQ009 = adjust & !clk1 & !c_state0 & c_state1 & !modes2
# !adjust & clk1 & c_state1 & !modes2
# clk1 & c_state0 & !modes2;
-- Node name is 'modes0'
-- Equation name is 'modes0', location is LC020, type is output.
modes0 = LCELL( _EQ010 $ c_state0);
_EQ010 = !c_state0 & c_state1 & modes2;
-- Node name is 'modes1'
-- Equation name is 'modes1', location is LC019, type is output.
modes1 = LCELL( _EQ011 $ c_state1);
_EQ011 = c_state1 & modes2;
-- Node name is 'modes2' = 'c_state2'
-- Equation name is 'modes2', location is LC017, type is output.
modes2 = DFFE( _EQ012 $ GND, GLOBAL( mode), !reset, VCC, VCC);
_EQ012 = c_state0 & c_state1 & !modes2
# !c_state0 & !c_state1 & modes2;
-- Node name is 'scl'
-- Equation name is 'scl', location is LC018, type is output.
scl = LCELL( _EQ013 $ GND);
_EQ013 = adjust & c_state0 & c_state1 & !modes2
# clk1 & !c_state0 & !c_state1
# clk1 & modes2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\taeyeon\alarm\mode_adjust.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,128K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -