📄 cnt24.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt24 IS
PORT(en,clk: IN STD_LOGIC;
qh,ql:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt24;
ARCHITECTURE arc OF cnt24 IS
SIGNAL ah,al:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
qh<=ah;
ql<=al;
PROCESS(en,clk)
BEGIN
IF(clk'EVENT AND clk='1')THEN
IF(en='1')THEN
IF(ah="0000" AND al="1001")THEN
ah<="0001";
al<="0000";
ELSIF(ah="0001" AND al="1001")THEN
ah<="0010";
al<="0000";
ELSIF(ah="0010" AND al="0011")THEN
ah<="0000";
al<="0000";
ELSE
al<=al+'1';
END IF;
END IF;
END IF;
END PROCESS;
END arc;
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