📄 cnt24.rpt
字号:
(32) 25 B SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\taeyeon\alarm\cnt24.rpt
cnt24
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------- LC26 |LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node2
| +----------------- LC25 |LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node3
| | +--------------- LC22 qh0
| | | +------------- LC20 qh1
| | | | +----------- LC19 qh2
| | | | | +--------- LC24 qh3
| | | | | | +------- LC23 ql0
| | | | | | | +----- LC17 ql1
| | | | | | | | +--- LC18 ql2
| | | | | | | | | +- LC21 ql3
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC26 -> - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node3
LC22 -> - - * * - - - - * * | - * | <-- qh0
LC20 -> - - * * - - - * * * | - * | <-- qh1
LC19 -> - - * * * - - * * * | - * | <-- qh2
LC24 -> - - * * - * - * * * | - * | <-- qh3
LC23 -> * * * * - - * * * * | - * | <-- ql0
LC17 -> * * * * - - - * * * | - * | <-- ql1
LC18 -> * * * * - - - * * * | - * | <-- ql2
LC21 -> - * * * - - - * * * | - * | <-- ql3
Pin
43 -> - - - - - - - - - - | - - | <-- clk
4 -> - - * * - - * * * * | - * | <-- en
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\taeyeon\alarm\cnt24.rpt
cnt24
** EQUATIONS **
clk : INPUT;
en : INPUT;
-- Node name is 'qh0' = 'ah0'
-- Equation name is 'qh0', location is LC022, type is output.
qh0 = TFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = en & !qh1 & !qh2 & !qh3 & ql0 & !ql1 & !ql2 & ql3;
-- Node name is 'qh1' = 'ah1'
-- Equation name is 'qh1', location is LC020, type is output.
qh1 = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = en & qh0 & !qh1 & !qh2 & !qh3 & ql0 & !ql1 & !ql2 & ql3
# en & !qh0 & qh1 & !qh2 & !qh3 & ql0 & ql1 & !ql2 & !ql3;
-- Node name is 'qh2' = 'ah2'
-- Equation name is 'qh2', location is LC019, type is output.
qh2 = TFFE( GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'qh3' = 'ah3'
-- Equation name is 'qh3', location is LC024, type is output.
qh3 = TFFE( GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'ql0' = 'al0'
-- Equation name is 'ql0', location is LC023, type is output.
ql0 = TFFE( en, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'ql1' = 'al1'
-- Equation name is 'ql1', location is LC017, type is output.
ql1 = TFFE(!_EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !qh1 & !qh2 & !qh3 & ql0 & !ql1 & !ql2 & ql3
# !ql0
# !en;
-- Node name is 'ql2' = 'al2'
-- Equation name is 'ql2', location is LC018, type is output.
ql2 = DFFE( _EQ004 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !qh0 & qh1 & !qh2 & !qh3 & ql0 & ql1 & !ql2 & !ql3
# !qh1 & !qh2 & !qh3 & ql0 & !ql1 & !ql2 & ql3
# en & !_LC026
# !en & !ql2;
-- Node name is 'ql3' = 'al3'
-- Equation name is 'ql3', location is LC021, type is output.
ql3 = DFFE( _EQ005 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !qh0 & qh1 & !qh2 & !qh3 & ql0 & ql1 & !ql2 & !ql3
# en & !qh1 & !qh2 & !qh3 & ql0 & !ql1 & !ql2 & ql3
# en & !_LC025
# !en & !ql3;
-- Node name is '|LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( ql2 $ _EQ006);
_EQ006 = ql0 & ql1;
-- Node name is '|LPM_ADD_SUB:200|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( ql3 $ _EQ007);
_EQ007 = ql0 & ql1 & ql2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\taeyeon\alarm\cnt24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,512K
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