📄 mode_adjust.vhd
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mode_adjust IS
PORT(mode,adjust,clk1,reset:IN STD_LOGIC;
enh,enm,ens,hcl,mcl,scl,ahc,amc:OUT STD_LOGIC;
modes:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END mode_adjust;
ARCHITECTURE arc OF mode_adjust IS
TYPE mystate IS (NORMAL,ADJUSTH,ADJUSTM,ADJUSTS,ADJUSTAH,ADJUSTAM);
SIGNAL c_state,n_state:mystate;
BEGIN
PROCESS(c_state)
BEGIN
CASE c_state IS
WHEN NORMAL=>
n_state<=ADJUSTH;
hcl<=clk1;
mcl<=clk1;
scl<=clk1;
enh<='0';
enm<='0';
ens<='0';
ahc<='0';
amc<='0';
modes<="000";
WHEN ADJUSTH=>
n_state<=ADJUSTM;
hcl<=adjust;
mcl<='0';
scl<='0';
enh<='1';
enm<='0';
ens<='0';
ahc<='0';
amc<='0';
modes<="001";
WHEN ADJUSTM=>
n_state<=ADJUSTS;
hcl<='0';
mcl<=adjust;
scl<='0';
enh<='0';
enm<='1';
ens<='0';
ahc<='0';
amc<='0';
modes<="010";
WHEN ADJUSTS=>
n_state<=ADJUSTAH;
hcl<='0';
mcl<='0';
scl<=adjust;
enh<='0';
enm<='0';
ens<='1';
ahc<='0';
amc<='0';
modes<="011";
WHEN ADJUSTAH=>
n_state<=ADJUSTAM;
hcl<=clk1;
mcl<=clk1;
scl<=clk1;
enh<='0';
enm<='0';
ens<='0';
ahc<=adjust;
amc<='0';
modes<="100";
WHEN ADJUSTAM=>
n_state<=NORMAL;
hcl<=clk1;
mcl<=clk1;
scl<=clk1;
enh<='0';
enm<='0';
ens<='0';
ahc<='0';
amc<=adjust;
modes<="101";
END CASE;
END PROCESS;
PROCESS(reset,mode)
BEGIN
IF(reset='1')THEN
c_state<=NORMAL;
ELSIF(mode'EVENT AND mode='1')THEN
c_state<=n_state;
END IF;
END PROCESS;
END arc;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -