📄 seg4_7.vhd
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY seg4_7 IS
PORT(data:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END seg4_7;
ARCHITECTURE arc OF seg4_7 IS
BEGIN
PROCESS(data)
BEGIN
CASE data IS
WHEN "0000"=>q<="1111110";
WHEN "0001"=>q<="0110000";
WHEN "0010"=>q<="1101101";
WHEN "0011"=>q<="1111001";
WHEN "0100"=>q<="0110011";
WHEN "0101"=>q<="1011011";
WHEN "0110"=>q<="1011111";
WHEN "0111"=>q<="1110000";
WHEN "1000"=>q<="1111111";
WHEN "1001"=>q<="1111011";
WHEN OTHERS =>q<="0000000";
END CASE;
END PROCESS;
END arc;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -