muxcmp.rpt

1．6个数码管动态扫描显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求有闹钟定闹

-- Node name is '~576~1' 
-- Equation name is '~576~1', location is LC010, type is buried.
-- synthesized logic cell 
_LC010   = LCELL( _EQ014 $  VCC);
  _EQ014 = !AML3 &  s0 &  s1 &  s2
         # !AHL3 &  s0 & !s1 &  s2
         # !AMH3 & !s0 &  s1 &  s2
         # !AHH3 & !s0 & !s1 &  s2
         # !_LC044 & !s1 & !s2;

-- Node name is '~597~1' 
-- Equation name is '~597~1', location is LC043, type is buried.
-- synthesized logic cell 
_LC043   = LCELL( _EQ015 $  VCC);
  _EQ015 = !AML2 &  s0 &  s1 &  s2
         # !AHL2 &  s0 & !s1 &  s2
         # !AHH2 & !s0 & !s1 &  s2
         # !s0 &  s1 &  _X014
         # !_LC033 & !s1 & !s2;
  _X014  = EXP( AMH2 &  s2);

-- Node name is '~618~1' 
-- Equation name is '~618~1', location is LC059, type is buried.
-- synthesized logic cell 
_LC059   = LCELL( _EQ016 $  VCC);
  _EQ016 = !AHL1 &  s0 & !s1 &  s2
         # !AMH1 & !s0 &  s1 &  s2
         # !AHH1 & !s0 & !s1 &  s2
         #  s0 &  s1 &  _X015
         # !_LC058 & !s1 & !s2;
  _X015  = EXP( AML1 &  s2);

-- Node name is '~639~1' 
-- Equation name is '~639~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ017 $  VCC);
  _EQ017 = !AHL0 &  s0 & !s1 &  s2
         # !AHH0 & !s0 & !s1 &  s2
         # !AML0 &  s0 &  s1
         # !AMH0 & !s0 &  s1
         # !s2 &  _X016;
  _X016  = EXP( _LC055 & !s1);

-- Node name is '~653~1' 
-- Equation name is '~653~1', location is LC064, type is buried.
-- synthesized logic cell 
_LC064   = LCELL( _EQ018 $  GND);
  _EQ018 =  modes0 &  modes1 & !modes2;

-- Node name is '~660~1' 
-- Equation name is '~660~1', location is LC050, type is buried.
-- synthesized logic cell 
_LC050   = LCELL( _EQ019 $  GND);
  _EQ019 = !modes0 &  modes1 & !modes2;

-- Node name is '~667~1' 
-- Equation name is '~667~1', location is LC053, type is buried.
-- synthesized logic cell 
_LC053   = LCELL( _EQ020 $  GND);
  _EQ020 =  modes0 & !modes1 & !modes2;

-- Node name is '~674~1' 
-- Equation name is '~674~1', location is LC057, type is buried.
-- synthesized logic cell 
_LC057   = LCELL( _EQ021 $  GND);
  _EQ021 = !modes0 & !modes1 & !modes2;

-- Node name is '~676~1' 
-- Equation name is '~676~1', location is LC051, type is buried.
-- synthesized logic cell 
_LC051   = LCELL( _EQ022 $  VCC);
  _EQ022 = !_LC050 & !_LC053 & !_LC057 & !_LC064;

-- Node name is '~677~1' 
-- Equation name is '~677~1', location is LC044, type is buried.
-- synthesized logic cell 
_LC044   = LCELL( _EQ023 $ !_LC046);
  _EQ023 = !_LC046 & !modes2 & !SL3 &  s0 &  s1 &  s2
         # !_LC046 & !ML3 & !modes2 &  s0 & !s1 &  s2
         # !_LC046 & !modes2 & !SH3 & !s0 &  s1 &  s2
         # !HL3 & !_LC046 & !modes2 &  s0 & !s1 & !s2;

-- Node name is '~677~2' 
-- Equation name is '~677~2', location is LC046, type is buried.
-- synthesized logic cell 
_LC046   = LCELL( _EQ024 $  GND);
  _EQ024 = !MH3 & !modes2 & !s0 & !s1 &  s2
         # !HH3 & !modes2 & !s0 & !s1 & !s2
         # !_LC044 & !modes2 &  s1 & !s2
         # !_LC010 &  modes2;

-- Node name is '~683~1~2' 
-- Equation name is '~683~1~2', location is LC038, type is buried.
-- synthesized logic cell 
_LC038   = LCELL( _EQ025 $  GND);
  _EQ025 = !AHL2 & !AML2 & !_LC042 & !_LC054 &  s0 &  s2
         # !AHH2 & !AHL2 & !_LC042 & !_LC054 & !s1 &  s2
         # !AHH2 & !AHL2 & !_LC028 & !_LC033 & !_LC042 & !s1;

-- Node name is '~683~1~3' 
-- Equation name is '~683~1~3', location is LC042, type is buried.
-- synthesized logic cell 
_LC042   = LCELL( _EQ026 $  GND);
  _EQ026 = !_LC028 &  _LC051
         # !AMH2 & !_LC050 & !_LC053 & !_LC057 & !_LC064 & !s0 &  s1
         # !_LC050 & !_LC053 & !_LC057 & !_LC064 & !s0 &  s1 & !s2
         # !_LC033 & !_LC050 & !_LC053 & !_LC057 & !_LC064 & !s1 & !s2;

-- Node name is '~683~1' 
-- Equation name is '~683~1', location is LC033, type is buried.
-- synthesized logic cell 
_LC033   = LCELL( _EQ027 $ !_LC042);
  _EQ027 = !AML2 & !_LC042 & !_LC054 &  s0 &  s1 &  s2
         # !AHL2 & !_LC042 & !_LC054 &  s0 & !s1 &  s2
         # !AHH2 & !_LC042 & !_LC054 & !s0 & !s1 &  s2
         #  _LC038;

-- Node name is '~689~1~2' 
-- Equation name is '~689~1~2', location is LC062, type is buried.
-- synthesized logic cell 
_LC062   = LCELL( _EQ028 $  GND);
  _EQ028 = !AHH1 & !AHL1 & !_LC054 & !_LC061 & !s1 &  s2
         # !AHH1 & !AMH1 & !_LC054 & !_LC061 & !s0 &  s2
         # !AHH1 & !AHL1 & !_LC003 & !_LC058 & !_LC061 & !s1;

-- Node name is '~689~1~3' 
-- Equation name is '~689~1~3', location is LC054, type is buried.
-- synthesized logic cell 
_LC054   = LCELL( _EQ029 $  GND);
  _EQ029 =  modes0 &  modes1 & !modes2
         # !modes0 &  modes1 & !modes2
         #  modes0 & !modes1 & !modes2
         # !modes0 & !modes1 & !modes2;

-- Node name is '~689~1~4' 
-- Equation name is '~689~1~4', location is LC061, type is buried.
-- synthesized logic cell 
_LC061   = LCELL( _EQ030 $  GND);
  _EQ030 = !_LC003 &  _LC051
         # !AML1 & !_LC050 & !_LC053 & !_LC057 & !_LC064 &  s0 &  s1
         # !_LC050 & !_LC053 & !_LC057 & !_LC064 &  s0 &  s1 & !s2
         # !_LC050 & !_LC053 & !_LC057 & !_LC058 & !_LC064 & !s1 & !s2;

-- Node name is '~689~1' 
-- Equation name is '~689~1', location is LC058, type is buried.
-- synthesized logic cell 
_LC058   = LCELL( _EQ031 $ !_LC061);
  _EQ031 = !AHL1 & !_LC054 & !_LC061 &  s0 & !s1 &  s2
         # !AMH1 & !_LC054 & !_LC061 & !s0 &  s1 &  s2
         # !AHH1 & !_LC054 & !_LC061 & !s0 & !s1 &  s2
         #  _LC062;

-- Node name is '~695~1' 
-- Equation name is '~695~1', location is LC055, type is buried.
-- synthesized logic cell 
_LC055   = LCELL( _EQ032 $ !_LC056);
  _EQ032 = !AHL0 & !_LC054 & !_LC056 &  s0 & !s1 &  s2
         # !AHH0 & !_LC054 & !_LC056 & !s0 & !s1 &  s2
         # !AML0 & !_LC054 & !_LC056 &  s0 &  s1
         # !AHH0 & !AHL0 & !_LC019 & !_LC056 & !s1 &  s2;

-- Node name is '~695~2' 
-- Equation name is '~695~2', location is LC056, type is buried.
-- synthesized logic cell 
_LC056   = LCELL( _EQ033 $  GND);
  _EQ033 = !_LC019 &  _LC051
         # !AMH0 & !_LC050 & !_LC053 & !_LC057 & !_LC064 & !s0 &  s1
         # !_LC050 & !_LC053 & !_LC057 & !_LC064 &  s1 & !s2
         # !_LC050 & !_LC053 & !_LC055 & !_LC057 & !_LC064 & !s2;

-- Node name is '~816~1' 
-- Equation name is '~816~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ034 $  _EQ035);
  _EQ034 = !AML0 & !_LC002 & !_LC009 & !_LC021 & !_LC026 & !_LC029 & !_LC039 & 
              ML0
         #  AML0 & !_LC002 & !_LC009 & !_LC021 & !_LC026 & !_LC029 & !_LC039 & 
             !ML0
         # !AML1 & !_LC002 & !_LC009 & !_LC021 & !_LC026 & !_LC029 & !_LC039 & 
              ML1
         #  AML1 & !_LC002 & !_LC009 & !_LC021 & !_LC026 & !_LC029 & !_LC039 & 
             !ML1;
  _EQ035 = !_LC002 & !_LC009 & !_LC021 & !_LC026 & !_LC029 & !_LC039;

-- Node name is '~816~2' 
-- Equation name is '~816~2', location is LC026, type is buried.
-- synthesized logic cell 
_LC026   = LCELL( _EQ036 $  GND);
  _EQ036 = !AML2 &  ML2
         #  AML2 & !ML2
         # !AML3 &  ML3
         #  AML3 & !ML3
         # !AMH0 &  MH0;

-- Node name is '~816~3' 
-- Equation name is '~816~3', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ037 $  GND);
  _EQ037 =  AMH0 & !MH0
         # !AMH1 &  MH1
         #  AMH1 & !MH1
         # !AMH2 &  MH2
         #  AMH2 & !MH2;

-- Node name is '~816~4' 
-- Equation name is '~816~4', location is LC009, type is buried.
-- synthesized logic cell 
_LC009   = LCELL( _EQ038 $  GND);
  _EQ038 = !AMH3 &  MH3
         #  AMH3 & !MH3
         # !AHL0 &  HL0
         #  AHL0 & !HL0
         # !AHL1 &  HL1;

-- Node name is '~816~5' 
-- Equation name is '~816~5', location is LC002, type is buried.
-- synthesized logic cell 
_LC002   = LCELL( _EQ039 $  GND);
  _EQ039 =  AHL1 & !HL1
         # !AHL2 &  HL2
         #  AHL2 & !HL2
         # !AHL3 &  HL3
         #  AHL3 & !HL3;

-- Node name is '~816~6' 
-- Equation name is '~816~6', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ040 $  GND);
  _EQ040 = !AHH0 &  HH0
         #  AHH0 & !HH0
         # !AHH1 &  HH1
         #  AHH1 & !HH1
         # !AHH2 &  HH2;

-- Node name is '~816~7' 
-- Equation name is '~816~7', location is LC039, type is buried.
-- synthesized logic cell 
_LC039   = LCELL( _EQ041 $  GND);
  _EQ041 =  AHH2 & !HH2
         # !AHH3 &  HH3
         #  AHH3 & !HH3;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs C, D




Project Information                                        g:\alarm\muxcmp.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:03
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,110K