📄 muxcmp.rpt
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- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------- LC28 ~342~1
| +--------- LC19 ~384~1
| | +------- LC17 ~639~1
| | | +----- LC26 ~816~2
| | | | +--- LC29 ~816~3
| | | | | +- LC21 ~816~6
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'B'
LC | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
32 -> - - * - - * | - * - * | <-- AHH0
33 -> - - - - - * | - * - * | <-- AHH1
59 -> - - - - - * | - * * - | <-- AHH2
13 -> - - * - - - | * * - * | <-- AHL0
27 -> - - * * * - | - * - * | <-- AMH0
28 -> - - - - * - | - * - * | <-- AMH1
29 -> - - - - * - | - * * - | <-- AMH2
14 -> - - * - - - | * * - * | <-- AML0
10 -> - - - * - - | - * * - | <-- AML2
9 -> - - - * - - | * * - - | <-- AML3
49 -> - * - - - * | - * - - | <-- HH0
7 -> - - - - - * | * * - - | <-- HH1
5 -> * - - - - * | - * * - | <-- HH2
45 -> - * - - - - | * * - - | <-- HL0
4 -> * - - - - - | * * - - | <-- HL2
36 -> - * - * * - | - * - - | <-- MH0
30 -> - - - - * - | * * - - | <-- MH1
19 -> * - - - * - | - * - - | <-- MH2
22 -> - * - - - - | * * - - | <-- ML0
1 -> - - - - - - | * - - - | <-- ML1
41 -> * - - * - - | - * - - | <-- ML2
20 -> - - - * - - | - * * - | <-- ML3
68 -> - - - - - - | - - - * | <-- modes1
2 -> - - - - - - | - - * * | <-- modes2
57 -> - * - - - - | - * - - | <-- SH0
52 -> * - - - - - | - * - - | <-- SH2
60 -> - * - - - - | - * - - | <-- SL0
67 -> - - - - - - | * - - - | <-- SL1
62 -> * - - - - - | - * - - | <-- SL2
15 -> * * * - - - | * * * * | <-- s0
17 -> * * * - - - | * * * * | <-- s1
18 -> * * * - - - | * * * * | <-- s2
LC33 -> * - - - - - | - * * - | <-- ~683~1
LC55 -> - * * - - - | - * - * | <-- ~695~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------- LC35 muxout2
| +----------------- LC41 muxout3
| | +--------------- LC48 ~321~1
| | | +------------- LC43 ~597~1
| | | | +----------- LC44 ~677~1
| | | | | +--------- LC46 ~677~2
| | | | | | +------- LC38 ~683~1~2
| | | | | | | +----- LC42 ~683~1~3
| | | | | | | | +--- LC33 ~683~1
| | | | | | | | | +- LC39 ~816~7
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC48 -> - * - - - - - - - - | - - * - | <-- ~321~1
LC43 -> * - - - - - - - - - | - - * - | <-- ~597~1
LC44 -> - - * - - * - - - - | * - * - | <-- ~677~1
LC46 -> - - - - * - - - - - | - - * - | <-- ~677~2
LC38 -> - - - - - - - - * - | - - * - | <-- ~683~1~2
LC42 -> - - - - - - * - * - | - - * - | <-- ~683~1~3
LC33 -> - - - * - - * * - - | - * * - | <-- ~683~1
Pin
59 -> - - - * - - * - * * | - * * - | <-- AHH2
46 -> - - - - - - - - - * | * - * - | <-- AHH3
23 -> - - - * - - * - * - | * - * - | <-- AHL2
29 -> - - - * - - - * - - | - * * - | <-- AMH2
10 -> - - - * - - * - * - | - * * - | <-- AML2
5 -> - - - - - - - - - * | - * * - | <-- HH2
47 -> - - * - - * - - - * | - - * - | <-- HH3
8 -> - - * - * - - - - - | * - * - | <-- HL3
25 -> - - * - - * - - - - | * - * - | <-- MH3
1 -> - - - - - - - - - - | * - - - | <-- ML1
20 -> - - * - * - - - - - | - * * - | <-- ML3
68 -> - - - - - - - - - - | - - - * | <-- modes1
2 -> - - - - * * - - - - | - - * * | <-- modes2
39 -> - - * - * - - - - - | - - * - | <-- SH3
67 -> - - - - - - - - - - | * - - - | <-- SL1
65 -> - - * - * - - - - - | - - * - | <-- SL3
15 -> - - * * * * * * * - | * * * * | <-- s0
17 -> - - * * * * * * * - | * * * * | <-- s1
18 -> - - * * * * * * * - | * * * * | <-- s2
LC28 -> * - - - - - * * - - | - - * - | <-- ~342~1
LC10 -> - * - - - * - - - - | - - * - | <-- ~576~1
LC64 -> * * - - - - - * - - | - - * * | <-- ~653~1
LC50 -> * * - - - - - * - - | - - * * | <-- ~660~1
LC53 -> * * - - - - - * - - | - - * * | <-- ~667~1
LC57 -> * * - - - - - * - - | - - * * | <-- ~674~1
LC51 -> - - - - - - - * - - | - - * * | <-- ~676~1
LC54 -> * * - - - - * - * - | - - * * | <-- ~689~1~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC52 alarm
| +--------------------------- LC60 muxout0
| | +------------------------- LC49 muxout1
| | | +----------------------- LC59 ~618~1
| | | | +--------------------- LC64 ~653~1
| | | | | +------------------- LC50 ~660~1
| | | | | | +----------------- LC53 ~667~1
| | | | | | | +--------------- LC57 ~674~1
| | | | | | | | +------------- LC51 ~676~1
| | | | | | | | | +----------- LC62 ~689~1~2
| | | | | | | | | | +--------- LC54 ~689~1~3
| | | | | | | | | | | +------- LC61 ~689~1~4
| | | | | | | | | | | | +----- LC58 ~689~1
| | | | | | | | | | | | | +--- LC55 ~695~1
| | | | | | | | | | | | | | +- LC56 ~695~2
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC59 -> - - * - - - - - - - - - - - - | - - - * | <-- ~618~1
LC64 -> - * * - - - - - * - - * - - * | - - * * | <-- ~653~1
LC50 -> - * * - - - - - * - - * - - * | - - * * | <-- ~660~1
LC53 -> - * * - - - - - * - - * - - * | - - * * | <-- ~667~1
LC57 -> - * * - - - - - * - - * - - * | - - * * | <-- ~674~1
LC51 -> - - - - - - - - - - - * - - * | - - * * | <-- ~676~1
LC62 -> - - - - - - - - - - - - * - - | - - - * | <-- ~689~1~2
LC54 -> - * * - - - - - - * - - * * - | - - * * | <-- ~689~1~3
LC61 -> - - - - - - - - - * - - * - - | - - - * | <-- ~689~1~4
LC58 -> - - - * - - - - - * - * - - - | * - - * | <-- ~689~1
LC55 -> - - - - - - - - - - - - - - * | - * - * | <-- ~695~1
LC56 -> - - - - - - - - - - - - - * - | - - - * | <-- ~695~2
Pin
32 -> - - - - - - - - - - - - - * - | - * - * | <-- AHH0
33 -> - - - * - - - - - * - - * - - | - * - * | <-- AHH1
13 -> - - - - - - - - - - - - - * - | * * - * | <-- AHL0
24 -> - - - * - - - - - * - - * - - | * - - * | <-- AHL1
27 -> - - - - - - - - - - - - - - * | - * - * | <-- AMH0
28 -> - - - * - - - - - * - - * - - | - * - * | <-- AMH1
14 -> - - - - - - - - - - - - - * - | * * - * | <-- AML0
12 -> - - - * - - - - - - - * - - - | * - - * | <-- AML1
56 -> * - - - - - - - - - - - - - - | - - - * | <-- clk
1 -> - - - - - - - - - - - - - - - | * - - - | <-- ML1
50 -> - - - - * * * * - - * - - - - | - - - * | <-- modes0
68 -> - - - - * * * * - - * - - - - | - - - * | <-- modes1
2 -> - - - - * * * * - - * - - - - | - - * * | <-- modes2
67 -> - - - - - - - - - - - - - - - | * - - - | <-- SL1
15 -> - - - * - - - - - * - * * * * | * * * * | <-- s0
17 -> - - - * - - - - - * - * * * * | * * * * | <-- s1
18 -> - - - * - - - - - * - * * * * | * * * * | <-- s2
LC3 -> - - * - - - - - - * - * - - - | - - - * | <-- ~363~1
LC19 -> - * - - - - - - - - - - - * * | - - - * | <-- ~384~1
LC17 -> - * - - - - - - - - - - - - - | - - - * | <-- ~639~1
LC1 -> * - - - - - - - - - - - - - - | - - - * | <-- ~816~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** EQUATIONS **
AHH0 : INPUT;
AHH1 : INPUT;
AHH2 : INPUT;
AHH3 : INPUT;
AHL0 : INPUT;
AHL1 : INPUT;
AHL2 : INPUT;
AHL3 : INPUT;
AMH0 : INPUT;
AMH1 : INPUT;
AMH2 : INPUT;
AMH3 : INPUT;
AML0 : INPUT;
AML1 : INPUT;
AML2 : INPUT;
AML3 : INPUT;
clk : INPUT;
HH0 : INPUT;
HH1 : INPUT;
HH2 : INPUT;
HH3 : INPUT;
HL0 : INPUT;
HL1 : INPUT;
HL2 : INPUT;
HL3 : INPUT;
MH0 : INPUT;
MH1 : INPUT;
MH2 : INPUT;
MH3 : INPUT;
ML0 : INPUT;
ML1 : INPUT;
ML2 : INPUT;
ML3 : INPUT;
modes0 : INPUT;
modes1 : INPUT;
modes2 : INPUT;
SH0 : INPUT;
SH1 : INPUT;
SH2 : INPUT;
SH3 : INPUT;
SL0 : INPUT;
SL1 : INPUT;
SL2 : INPUT;
SL3 : INPUT;
s0 : INPUT;
s1 : INPUT;
s2 : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', location is LC052, type is output.
alarm = LCELL( _EQ001 $ GND);
_EQ001 = clk & _LC001;
-- Node name is 'muxout0'
-- Equation name is 'muxout0', location is LC060, type is output.
muxout0 = LCELL( _EQ002 $ GND);
_EQ002 = _LC017 & !_LC054
# _LC019 & _X001;
_X001 = EXP(!_LC050 & !_LC053 & !_LC057 & !_LC064);
-- Node name is 'muxout1'
-- Equation name is 'muxout1', location is LC049, type is output.
muxout1 = LCELL( _EQ003 $ GND);
_EQ003 = !_LC054 & _LC059
# _LC003 & _X001;
_X001 = EXP(!_LC050 & !_LC053 & !_LC057 & !_LC064);
-- Node name is 'muxout2'
-- Equation name is 'muxout2', location is LC035, type is output.
muxout2 = LCELL( _EQ004 $ GND);
_EQ004 = _LC043 & !_LC054
# _LC028 & _X001;
_X001 = EXP(!_LC050 & !_LC053 & !_LC057 & !_LC064);
-- Node name is 'muxout3'
-- Equation name is 'muxout3', location is LC041, type is output.
muxout3 = LCELL( _EQ005 $ GND);
_EQ005 = _LC010 & !_LC054
# _LC048 & _X001;
_X001 = EXP(!_LC050 & !_LC053 & !_LC057 & !_LC064);
-- Node name is '~321~1'
-- Equation name is '~321~1', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ006 $ _EQ007);
_EQ006 = !SL3 & s0 & s1 & s2 & _X002 & _X003 & _X004
# !ML3 & s0 & !s1 & s2 & _X002 & _X003 & _X004
# !SH3 & !s0 & s1 & s2 & _X002 & _X003 & _X004
# !HL3 & s0 & !s1 & !s2 & _X002 & _X003 & _X004;
_X002 = EXP(!HH3 & !s0 & !s1 & !s2);
_X003 = EXP(!MH3 & !s0 & !s1 & s2);
_X004 = EXP(!_LC044 & s1 & !s2);
_EQ007 = _X002 & _X003 & _X004;
_X002 = EXP(!HH3 & !s0 & !s1 & !s2);
_X003 = EXP(!MH3 & !s0 & !s1 & s2);
_X004 = EXP(!_LC044 & s1 & !s2);
-- Node name is '~342~1'
-- Equation name is '~342~1', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ008 $ _EQ009);
_EQ008 = !SL2 & s0 & s1 & s2 & _X005 & _X006 & _X007
# !ML2 & s0 & !s1 & s2 & _X005 & _X006 & _X007
# !SH2 & !s0 & s1 & s2 & _X005 & _X006 & _X007
# !HL2 & s0 & !s1 & !s2 & _X005 & _X006 & _X007;
_X005 = EXP(!HH2 & !s0 & !s1 & !s2);
_X006 = EXP(!MH2 & !s0 & !s1 & s2);
_X007 = EXP(!_LC033 & s1 & !s2);
_EQ009 = _X005 & _X006 & _X007;
_X005 = EXP(!HH2 & !s0 & !s1 & !s2);
_X006 = EXP(!MH2 & !s0 & !s1 & s2);
_X007 = EXP(!_LC033 & s1 & !s2);
-- Node name is '~363~1'
-- Equation name is '~363~1', location is LC003, type is buried.
-- synthesized logic cell
_LC003 = LCELL( _EQ010 $ _EQ011);
_EQ010 = !SL1 & s0 & s1 & s2 & _X008 & _X009 & _X010
# !ML1 & s0 & !s1 & s2 & _X008 & _X009 & _X010
# !SH1 & !s0 & s1 & s2 & _X008 & _X009 & _X010
# !HL1 & s0 & !s1 & !s2 & _X008 & _X009 & _X010;
_X008 = EXP(!HH1 & !s0 & !s1 & !s2);
_X009 = EXP(!MH1 & !s0 & !s1 & s2);
_X010 = EXP(!_LC058 & s1 & !s2);
_EQ011 = _X008 & _X009 & _X010;
_X008 = EXP(!HH1 & !s0 & !s1 & !s2);
_X009 = EXP(!MH1 & !s0 & !s1 & s2);
_X010 = EXP(!_LC058 & s1 & !s2);
-- Node name is '~384~1'
-- Equation name is '~384~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ012 $ _EQ013);
_EQ012 = !SL0 & s0 & s1 & s2 & _X011 & _X012 & _X013
# !ML0 & s0 & !s1 & s2 & _X011 & _X012 & _X013
# !SH0 & !s0 & s1 & s2 & _X011 & _X012 & _X013
# !HL0 & s0 & !s1 & !s2 & _X011 & _X012 & _X013;
_X011 = EXP(!HH0 & !s0 & !s1 & !s2);
_X012 = EXP(!MH0 & !s0 & !s1 & s2);
_X013 = EXP(!_LC055 & s1 & !s2);
_EQ013 = _X011 & _X012 & _X013;
_X011 = EXP(!HH0 & !s0 & !s1 & !s2);
_X012 = EXP(!MH0 & !s0 & !s1 & s2);
_X013 = EXP(!_LC055 & s1 & !s2);
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