📄 muxcmp.rpt
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Project Information g:\alarm\muxcmp.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/05/2008 20:31:08
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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***** Project compilation was successful
MUXCMP
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
muxcmp EPM7064LC68-7 47 5 0 36 17 56 %
User Pins: 47 5 0
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
***** Logic for device 'muxcmp' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** ERROR SUMMARY **
Info: Chip 'muxcmp' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
m
V m m u
C o o V x
A C d d C o
M H H G H H I e M e S G S S C S u
L L H N H L N s L s L N L H I L t
3 3 1 D 2 2 T 2 1 1 1 D 3 1 O 2 0
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
AML2 | 10 60 | SL0
VCCIO | 11 59 | AHH2
AML1 | 12 58 | GND
AHL0 | 13 57 | SH0
AML0 | 14 56 | clk
s0 | 15 55 | AMH3
GND | 16 54 | alarm
s1 | 17 53 | VCCIO
s2 | 18 EPM7064LC68-7 52 | SH2
MH2 | 19 51 | muxout1
ML3 | 20 50 | modes0
VCCIO | 21 49 | HH0
ML0 | 22 48 | GND
AHL2 | 23 47 | HH3
AHL1 | 24 46 | AHH3
MH3 | 25 45 | HL0
GND | 26 44 | muxout3
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
A A A M V A A G V M m G S H M A V
M M M H C H H N C H u N H L L H C
H H H 1 C H H D C 0 x D 3 1 2 L C
0 1 2 I 0 1 I o 3 I
O N u O
T t
2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 12/12(100%) 8/16( 50%) 31/36( 86%)
B: LC17 - LC32 6/16( 37%) 12/12(100%) 13/16( 81%) 30/36( 83%)
C: LC33 - LC48 10/16( 62%) 12/12(100%) 9/16( 56%) 31/36( 86%)
D: LC49 - LC64 15/16( 93%) 12/12(100%) 5/16( 31%) 31/36( 86%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 48/48 (100%)
Total logic cells used: 36/64 ( 56%)
Total shareable expanders used: 17/64 ( 26%)
Total Turbo logic cells used: 36/64 ( 56%)
Total shareable expanders not available (n/a): 18/64 ( 28%)
Average fan-in: 7.27
Total fan-in: 262
Total input pins required: 47
Total output pins required: 5
Total bidirectional pins required: 0
Total logic cells required: 36
Total flipflops required: 0
Total product terms required: 150
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 16
Synthesized logic cells: 31/ 64 ( 48%)
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 (19) (B) INPUT 0 0 0 0 0 0 3 AHH0
33 (17) (B) INPUT 0 0 0 0 0 0 4 AHH1
59 (57) (D) INPUT 0 0 0 0 0 0 5 AHH2
46 (44) (C) INPUT 0 0 0 0 0 0 2 AHH3
13 (6) (A) INPUT 0 0 0 0 0 0 3 AHL0
24 (27) (B) INPUT 0 0 0 0 0 0 5 AHL1
23 (28) (B) INPUT 0 0 0 0 0 0 4 AHL2
42 (40) (C) INPUT 0 0 0 0 0 0 2 AHL3
27 (24) (B) INPUT 0 0 0 0 0 0 4 AMH0
28 (22) (B) INPUT 0 0 0 0 0 0 4 AMH1
29 (21) (B) INPUT 0 0 0 0 0 0 3 AMH2
55 (53) (D) INPUT 0 0 0 0 0 0 2 AMH3
14 (5) (A) INPUT 0 0 0 0 0 0 3 AML0
12 (8) (A) INPUT 0 0 0 0 0 0 3 AML1
10 (9) (A) INPUT 0 0 0 0 0 0 4 AML2
9 (11) (A) INPUT 0 0 0 0 0 0 2 AML3
56 (54) (D) INPUT 0 0 0 0 0 1 0 clk
49 (46) (C) INPUT 0 0 0 0 0 0 2 HH0
7 (13) (A) INPUT 0 0 0 0 0 0 2 HH1
5 (14) (A) INPUT 0 0 0 0 0 0 3 HH2
47 (45) (C) INPUT 0 0 0 0 0 0 3 HH3
45 (43) (C) INPUT 0 0 0 0 0 0 2 HL0
40 (37) (C) INPUT 0 0 0 0 0 0 3 HL1
4 (16) (A) INPUT 0 0 0 0 0 0 2 HL2
8 (12) (A) INPUT 0 0 0 0 0 0 3 HL3
36 (33) (C) INPUT 0 0 0 0 0 0 3 MH0
30 (20) (B) INPUT 0 0 0 0 0 0 2 MH1
19 (32) (B) INPUT 0 0 0 0 0 0 2 MH2
25 (25) (B) INPUT 0 0 0 0 0 0 3 MH3
22 (29) (B) INPUT 0 0 0 0 0 0 2 ML0
1 - - INPUT 0 0 0 0 0 0 2 ML1
41 (38) (C) INPUT 0 0 0 0 0 0 2 ML2
20 (30) (B) INPUT 0 0 0 0 0 0 3 ML3
50 (48) (C) INPUT 0 0 0 0 0 0 5 modes0
68 - - INPUT 0 0 0 0 0 0 5 modes1
2 - - INPUT 0 0 0 0 0 0 7 modes2
57 (56) (D) INPUT 0 0 0 0 0 0 1 SH0
64 (62) (D) INPUT 0 0 0 0 0 0 1 SH1
52 (51) (D) INPUT 0 0 0 0 0 0 1 SH2
39 (36) (C) INPUT 0 0 0 0 0 0 2 SH3
60 (59) (D) INPUT 0 0 0 0 0 0 1 SL0
67 - - INPUT 0 0 0 0 0 0 1 SL1
62 (61) (D) INPUT 0 0 0 0 0 0 1 SL2
65 (64) (D) INPUT 0 0 0 0 0 0 2 SL3
15 (4) (A) INPUT 0 0 0 0 0 0 18 s0
17 (3) (A) INPUT 0 0 0 0 0 0 18 s1
18 (1) (A) INPUT 0 0 0 0 0 0 18 s2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
54 52 D OUTPUT t 0 0 0 1 1 0 0 alarm
61 60 D OUTPUT t 1 1 0 0 7 0 0 muxout0
51 49 D OUTPUT t 1 1 0 0 7 0 0 muxout1
37 35 C OUTPUT t 1 1 0 0 7 0 0 muxout2
44 41 C OUTPUT t 1 1 0 0 7 0 0 muxout3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(50) 48 C SOFT s t 4 0 1 9 1 1 0 ~321~1
(23) 28 B SOFT s t 4 0 1 9 1 1 2 ~342~1
(17) 3 A SOFT s t 4 0 1 9 1 1 2 ~363~1
(32) 19 B SOFT s t 4 0 1 9 1 1 2 ~384~1
- 10 A SOFT s t 1 0 1 7 1 1 1 ~576~1
(45) 43 C SOFT s t 2 0 1 7 1 1 0 ~597~1
(60) 59 D SOFT s t 2 0 1 7 1 1 0 ~618~1
(33) 17 B SOFT s t 2 0 1 7 1 1 0 ~639~1
(65) 64 D SOFT s t 0 0 0 3 0 4 4 ~653~1
- 50 D SOFT s t 0 0 0 3 0 4 4 ~660~1
(55) 53 D SOFT s t 0 0 0 3 0 4 4 ~667~1
(59) 57 D SOFT s t 0 0 0 3 0 4 4 ~674~1
(52) 51 D SOFT s t 0 0 0 0 4 0 3 ~676~1
(46) 44 C LCELL s t 1 0 1 8 1 0 3 ~677~1
(49) 46 C SOFT s t 0 0 0 6 2 0 1 ~677~2
(41) 38 C LCELL s t 0 0 0 6 4 0 1 ~683~1~2
- 42 C SOFT s t 0 0 0 4 7 0 2 ~683~1~3
(36) 33 C LCELL s t 1 0 1 6 3 0 4 ~683~1
(64) 62 D LCELL s t 0 0 0 6 4 0 1 ~689~1~2
(56) 54 D SOFT s t 0 0 0 3 0 4 5 ~689~1~3
(62) 61 D SOFT s t 0 0 0 4 7 0 2 ~689~1~4
- 58 D LCELL s t 1 0 1 6 3 0 4 ~689~1
- 55 D LCELL s t 1 0 1 6 3 0 3 ~695~1
(57) 56 D SOFT s t 0 0 0 4 7 0 1 ~695~2
(18) 1 A SOFT s t 1 0 1 4 6 1 0 ~816~1
- 26 B SOFT s t 1 0 1 6 0 0 1 ~816~2
(22) 29 B SOFT s t 1 0 1 6 0 0 1 ~816~3
(10) 9 A SOFT s t 1 0 1 6 0 0 1 ~816~4
- 2 A SOFT s t 1 0 1 6 0 0 1 ~816~5
(29) 21 B SOFT s t 1 0 1 6 0 0 1 ~816~6
- 39 C SOFT s t 0 0 0 4 0 0 1 ~816~7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\alarm\muxcmp.rpt
muxcmp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC3 ~363~1
| +------- LC10 ~576~1
| | +----- LC1 ~816~1
| | | +--- LC9 ~816~4
| | | | +- LC2 ~816~5
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B C D | Logic cells that feed LAB 'A':
LC9 -> - - * - - | * - - - | <-- ~816~4
LC2 -> - - * - - | * - - - | <-- ~816~5
Pin
46 -> - * - - - | * - * - | <-- AHH3
13 -> - - - * - | * * - * | <-- AHL0
24 -> - - - * * | * - - * | <-- AHL1
23 -> - - - - * | * - * - | <-- AHL2
42 -> - * - - * | * - - - | <-- AHL3
55 -> - * - * - | * - - - | <-- AMH3
14 -> - - * - - | * * - * | <-- AML0
12 -> - - * - - | * - - * | <-- AML1
9 -> - * - - - | * * - - | <-- AML3
7 -> * - - - - | * * - - | <-- HH1
45 -> - - - * - | * * - - | <-- HL0
40 -> * - - * * | * - - - | <-- HL1
4 -> - - - - * | * * - - | <-- HL2
8 -> - - - - * | * - * - | <-- HL3
30 -> * - - - - | * * - - | <-- MH1
25 -> - - - * - | * - * - | <-- MH3
22 -> - - * - - | * * - - | <-- ML0
1 -> * - * - - | * - - - | <-- ML1
68 -> - - - - - | - - - * | <-- modes1
2 -> - - - - - | - - * * | <-- modes2
64 -> * - - - - | * - - - | <-- SH1
67 -> * - - - - | * - - - | <-- SL1
15 -> * * - - - | * * * * | <-- s0
17 -> * * - - - | * * * * | <-- s1
18 -> * * - - - | * * * * | <-- s2
LC44 -> - * - - - | * - * - | <-- ~677~1
LC58 -> * - - - - | * - - * | <-- ~689~1
LC26 -> - - * - - | * - - - | <-- ~816~2
LC29 -> - - * - - | * - - - | <-- ~816~3
LC21 -> - - * - - | * - - - | <-- ~816~6
LC39 -> - - * - - | * - - - | <-- ~816~7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
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