phase_shift_sin.map.eqn

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· EQN 代码 · 共 868 行 · 第 1/5 页

RB1_q_b[3]_PORT_B_write_enable_reg = DFFE(RB1_q_b[3]_PORT_B_write_enable, RB1_q_b[3]_clock_1, , , );
RB1_q_b[3]_clock_0 = clk;
RB1_q_b[3]_clock_1 = A1L5;
RB1_q_b[3]_PORT_B_data_out = MEMORY(RB1_q_b[3]_PORT_A_data_in_reg, RB1_q_b[3]_PORT_B_data_in_reg, RB1_q_b[3]_PORT_A_address_reg, RB1_q_b[3]_PORT_B_address_reg, RB1_q_b[3]_PORT_A_write_enable_reg, RB1_q_b[3]_PORT_B_write_enable_reg, , , RB1_q_b[3]_clock_0, RB1_q_b[3]_clock_1, , , , );
RB1_q_b[3] = RB1_q_b[3]_PORT_B_data_out[0];


--RB1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[4]_PORT_A_data_in = VCC;
RB1_q_a[4]_PORT_A_data_in_reg = DFFE(RB1_q_a[4]_PORT_A_data_in, RB1_q_a[4]_clock_0, , , );
RB1_q_a[4]_PORT_B_data_in = SB1_ram_rom_data_reg[4];
RB1_q_a[4]_PORT_B_data_in_reg = DFFE(RB1_q_a[4]_PORT_B_data_in, RB1_q_a[4]_clock_1, , , );
RB1_q_a[4]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[4]_PORT_A_address_reg = DFFE(RB1_q_a[4]_PORT_A_address, RB1_q_a[4]_clock_0, , , );
RB1_q_a[4]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[4]_PORT_B_address_reg = DFFE(RB1_q_a[4]_PORT_B_address, RB1_q_a[4]_clock_1, , , );
RB1_q_a[4]_PORT_A_write_enable = GND;
RB1_q_a[4]_PORT_A_write_enable_reg = DFFE(RB1_q_a[4]_PORT_A_write_enable, RB1_q_a[4]_clock_0, , , );
RB1_q_a[4]_PORT_B_write_enable = SB1L2;
RB1_q_a[4]_PORT_B_write_enable_reg = DFFE(RB1_q_a[4]_PORT_B_write_enable, RB1_q_a[4]_clock_1, , , );
RB1_q_a[4]_clock_0 = clk;
RB1_q_a[4]_clock_1 = A1L5;
RB1_q_a[4]_PORT_A_data_out = MEMORY(RB1_q_a[4]_PORT_A_data_in_reg, RB1_q_a[4]_PORT_B_data_in_reg, RB1_q_a[4]_PORT_A_address_reg, RB1_q_a[4]_PORT_B_address_reg, RB1_q_a[4]_PORT_A_write_enable_reg, RB1_q_a[4]_PORT_B_write_enable_reg, , , RB1_q_a[4]_clock_0, RB1_q_a[4]_clock_1, , , , );
RB1_q_a[4]_PORT_A_data_out_reg = DFFE(RB1_q_a[4]_PORT_A_data_out, RB1_q_a[4]_clock_0, , , );
RB1_q_a[4] = RB1_q_a[4]_PORT_A_data_out_reg[0];

--RB1_q_b[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[4]
RB1_q_b[4]_PORT_A_data_in = VCC;
RB1_q_b[4]_PORT_A_data_in_reg = DFFE(RB1_q_b[4]_PORT_A_data_in, RB1_q_b[4]_clock_0, , , );
RB1_q_b[4]_PORT_B_data_in = SB1_ram_rom_data_reg[4];
RB1_q_b[4]_PORT_B_data_in_reg = DFFE(RB1_q_b[4]_PORT_B_data_in, RB1_q_b[4]_clock_1, , , );
RB1_q_b[4]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[4]_PORT_A_address_reg = DFFE(RB1_q_b[4]_PORT_A_address, RB1_q_b[4]_clock_0, , , );
RB1_q_b[4]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[4]_PORT_B_address_reg = DFFE(RB1_q_b[4]_PORT_B_address, RB1_q_b[4]_clock_1, , , );
RB1_q_b[4]_PORT_A_write_enable = GND;
RB1_q_b[4]_PORT_A_write_enable_reg = DFFE(RB1_q_b[4]_PORT_A_write_enable, RB1_q_b[4]_clock_0, , , );
RB1_q_b[4]_PORT_B_write_enable = SB1L2;
RB1_q_b[4]_PORT_B_write_enable_reg = DFFE(RB1_q_b[4]_PORT_B_write_enable, RB1_q_b[4]_clock_1, , , );
RB1_q_b[4]_clock_0 = clk;
RB1_q_b[4]_clock_1 = A1L5;
RB1_q_b[4]_PORT_B_data_out = MEMORY(RB1_q_b[4]_PORT_A_data_in_reg, RB1_q_b[4]_PORT_B_data_in_reg, RB1_q_b[4]_PORT_A_address_reg, RB1_q_b[4]_PORT_B_address_reg, RB1_q_b[4]_PORT_A_write_enable_reg, RB1_q_b[4]_PORT_B_write_enable_reg, , , RB1_q_b[4]_clock_0, RB1_q_b[4]_clock_1, , , , );
RB1_q_b[4] = RB1_q_b[4]_PORT_B_data_out[0];


--RB1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[5]_PORT_A_data_in = VCC;
RB1_q_a[5]_PORT_A_data_in_reg = DFFE(RB1_q_a[5]_PORT_A_data_in, RB1_q_a[5]_clock_0, , , );
RB1_q_a[5]_PORT_B_data_in = SB1_ram_rom_data_reg[5];
RB1_q_a[5]_PORT_B_data_in_reg = DFFE(RB1_q_a[5]_PORT_B_data_in, RB1_q_a[5]_clock_1, , , );
RB1_q_a[5]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[5]_PORT_A_address_reg = DFFE(RB1_q_a[5]_PORT_A_address, RB1_q_a[5]_clock_0, , , );
RB1_q_a[5]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[5]_PORT_B_address_reg = DFFE(RB1_q_a[5]_PORT_B_address, RB1_q_a[5]_clock_1, , , );
RB1_q_a[5]_PORT_A_write_enable = GND;
RB1_q_a[5]_PORT_A_write_enable_reg = DFFE(RB1_q_a[5]_PORT_A_write_enable, RB1_q_a[5]_clock_0, , , );
RB1_q_a[5]_PORT_B_write_enable = SB1L2;
RB1_q_a[5]_PORT_B_write_enable_reg = DFFE(RB1_q_a[5]_PORT_B_write_enable, RB1_q_a[5]_clock_1, , , );
RB1_q_a[5]_clock_0 = clk;
RB1_q_a[5]_clock_1 = A1L5;
RB1_q_a[5]_PORT_A_data_out = MEMORY(RB1_q_a[5]_PORT_A_data_in_reg, RB1_q_a[5]_PORT_B_data_in_reg, RB1_q_a[5]_PORT_A_address_reg, RB1_q_a[5]_PORT_B_address_reg, RB1_q_a[5]_PORT_A_write_enable_reg, RB1_q_a[5]_PORT_B_write_enable_reg, , , RB1_q_a[5]_clock_0, RB1_q_a[5]_clock_1, , , , );
RB1_q_a[5]_PORT_A_data_out_reg = DFFE(RB1_q_a[5]_PORT_A_data_out, RB1_q_a[5]_clock_0, , , );
RB1_q_a[5] = RB1_q_a[5]_PORT_A_data_out_reg[0];

--RB1_q_b[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[5]
RB1_q_b[5]_PORT_A_data_in = VCC;
RB1_q_b[5]_PORT_A_data_in_reg = DFFE(RB1_q_b[5]_PORT_A_data_in, RB1_q_b[5]_clock_0, , , );
RB1_q_b[5]_PORT_B_data_in = SB1_ram_rom_data_reg[5];
RB1_q_b[5]_PORT_B_data_in_reg = DFFE(RB1_q_b[5]_PORT_B_data_in, RB1_q_b[5]_clock_1, , , );
RB1_q_b[5]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[5]_PORT_A_address_reg = DFFE(RB1_q_b[5]_PORT_A_address, RB1_q_b[5]_clock_0, , , );
RB1_q_b[5]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[5]_PORT_B_address_reg = DFFE(RB1_q_b[5]_PORT_B_address, RB1_q_b[5]_clock_1, , , );
RB1_q_b[5]_PORT_A_write_enable = GND;
RB1_q_b[5]_PORT_A_write_enable_reg = DFFE(RB1_q_b[5]_PORT_A_write_enable, RB1_q_b[5]_clock_0, , , );
RB1_q_b[5]_PORT_B_write_enable = SB1L2;
RB1_q_b[5]_PORT_B_write_enable_reg = DFFE(RB1_q_b[5]_PORT_B_write_enable, RB1_q_b[5]_clock_1, , , );
RB1_q_b[5]_clock_0 = clk;
RB1_q_b[5]_clock_1 = A1L5;
RB1_q_b[5]_PORT_B_data_out = MEMORY(RB1_q_b[5]_PORT_A_data_in_reg, RB1_q_b[5]_PORT_B_data_in_reg, RB1_q_b[5]_PORT_A_address_reg, RB1_q_b[5]_PORT_B_address_reg, RB1_q_b[5]_PORT_A_write_enable_reg, RB1_q_b[5]_PORT_B_write_enable_reg, , , RB1_q_b[5]_clock_0, RB1_q_b[5]_clock_1, , , , );
RB1_q_b[5] = RB1_q_b[5]_PORT_B_data_out[0];


--RB1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[6]_PORT_A_data_in = VCC;
RB1_q_a[6]_PORT_A_data_in_reg = DFFE(RB1_q_a[6]_PORT_A_data_in, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6]_PORT_B_data_in = SB1_ram_rom_data_reg[6];
RB1_q_a[6]_PORT_B_data_in_reg = DFFE(RB1_q_a[6]_PORT_B_data_in, RB1_q_a[6]_clock_1, , , );
RB1_q_a[6]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[6]_PORT_A_address_reg = DFFE(RB1_q_a[6]_PORT_A_address, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[6]_PORT_B_address_reg = DFFE(RB1_q_a[6]_PORT_B_address, RB1_q_a[6]_clock_1, , , );
RB1_q_a[6]_PORT_A_write_enable = GND;
RB1_q_a[6]_PORT_A_write_enable_reg = DFFE(RB1_q_a[6]_PORT_A_write_enable, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6]_PORT_B_write_enable = SB1L2;
RB1_q_a[6]_PORT_B_write_enable_reg = DFFE(RB1_q_a[6]_PORT_B_write_enable, RB1_q_a[6]_clock_1, , , );
RB1_q_a[6]_clock_0 = clk;
RB1_q_a[6]_clock_1 = A1L5;
RB1_q_a[6]_PORT_A_data_out = MEMORY(RB1_q_a[6]_PORT_A_data_in_reg, RB1_q_a[6]_PORT_B_data_in_reg, RB1_q_a[6]_PORT_A_address_reg, RB1_q_a[6]_PORT_B_address_reg, RB1_q_a[6]_PORT_A_write_enable_reg, RB1_q_a[6]_PORT_B_write_enable_reg, , , RB1_q_a[6]_clock_0, RB1_q_a[6]_clock_1, , , , );
RB1_q_a[6]_PORT_A_data_out_reg = DFFE(RB1_q_a[6]_PORT_A_data_out, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6] = RB1_q_a[6]_PORT_A_data_out_reg[0];

--RB1_q_b[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[6]
RB1_q_b[6]_PORT_A_data_in = VCC;
RB1_q_b[6]_PORT_A_data_in_reg = DFFE(RB1_q_b[6]_PORT_A_data_in, RB1_q_b[6]_clock_0, , , );
RB1_q_b[6]_PORT_B_data_in = SB1_ram_rom_data_reg[6];
RB1_q_b[6]_PORT_B_data_in_reg = DFFE(RB1_q_b[6]_PORT_B_data_in, RB1_q_b[6]_clock_1, , , );
RB1_q_b[6]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[6]_PORT_A_address_reg = DFFE(RB1_q_b[6]_PORT_A_address, RB1_q_b[6]_clock_0, , , );
RB1_q_b[6]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[6]_PORT_B_address_reg = DFFE(RB1_q_b[6]_PORT_B_address, RB1_q_b[6]_clock_1, , , );
RB1_q_b[6]_PORT_A_write_enable = GND;
RB1_q_b[6]_PORT_A_write_enable_reg = DFFE(RB1_q_b[6]_PORT_A_write_enable, RB1_q_b[6]_clock_0, , , );
RB1_q_b[6]_PORT_B_write_enable = SB1L2;
RB1_q_b[6]_PORT_B_write_enable_reg = DFFE(RB1_q_b[6]_PORT_B_write_enable, RB1_q_b[6]_clock_1, , , );
RB1_q_b[6]_clock_0 = clk;
RB1_q_b[6]_clock_1 = A1L5;
RB1_q_b[6]_PORT_B_data_out = MEMORY(RB1_q_b[6]_PORT_A_data_in_reg, RB1_q_b[6]_PORT_B_data_in_reg, RB1_q_b[6]_PORT_A_address_reg, RB1_q_b[6]_PORT_B_address_reg, RB1_q_b[6]_PORT_A_write_enable_reg, RB1_q_b[6]_PORT_B_write_enable_reg, , , RB1_q_b[6]_clock_0, RB1_q_b[6]_clock_1, , , , );
RB1_q_b[6] = RB1_q_b[6]_PORT_B_data_out[0];


--RB1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[7]_PORT_A_data_in = VCC;
RB1_q_a[7]_PORT_A_data_in_reg = DFFE(RB1_q_a[7]_PORT_A_data_in, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7]_PORT_B_data_in = SB1_ram_rom_data_reg[7];
RB1_q_a[7]_PORT_B_data_in_reg = DFFE(RB1_q_a[7]_PORT_B_data_in, RB1_q_a[7]_clock_1, , , );
RB1_q_a[7]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[7]_PORT_A_address_reg = DFFE(RB1_q_a[7]_PORT_A_address, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[7]_PORT_B_address_reg = DFFE(RB1_q_a[7]_PORT_B_address, RB1_q_a[7]_clock_1, , , );
RB1_q_a[7]_PORT_A_write_enable = GND;
RB1_q_a[7]_PORT_A_write_enable_reg = DFFE(RB1_q_a[7]_PORT_A_write_enable, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7]_PORT_B_write_enable = SB1L2;
RB1_q_a[7]_PORT_B_write_enable_reg = DFFE(RB1_q_a[7]_PORT_B_write_enable, RB1_q_a[7]_clock_1, , , );
RB1_q_a[7]_clock_0 = clk;
RB1_q_a[7]_clock_1 = A1L5;
RB1_q_a[7]_PORT_A_data_out = MEMORY(RB1_q_a[7]_PORT_A_data_in_reg, RB1_q_a[7]_PORT_B_data_in_reg, RB1_q_a[7]_PORT_A_address_reg, RB1_q_a[7]_PORT_B_address_reg, RB1_q_a[7]_PORT_A_write_enable_reg, RB1_q_a[7]_PORT_B_write_enable_reg, , , RB1_q_a[7]_clock_0, RB1_q_a[7]_clock_1, , , , );
RB1_q_a[7]_PORT_A_data_out_reg = DFFE(RB1_q_a[7]_PORT_A_data_out, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7] = RB1_q_a[7]_PORT_A_data_out_reg[0];

--RB1_q_b[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[7]
RB1_q_b[7]_PORT_A_data_in = VCC;
RB1_q_b[7]_PORT_A_data_in_reg = DFFE(RB1_q_b[7]_PORT_A_data_in, RB1_q_b[7]_clock_0, , , );
RB1_q_b[7]_PORT_B_data_in = SB1_ram_rom_data_reg[7];
RB1_q_b[7]_PORT_B_data_in_reg = DFFE(RB1_q_b[7]_PORT_B_data_in, RB1_q_b[7]_clock_1, , , );
RB1_q_b[7]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[7]_PORT_A_address_reg = DFFE(RB1_q_b[7]_PORT_A_address, RB1_q_b[7]_clock_0, , , );
RB1_q_b[7]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[7]_PORT_B_address_reg = DFFE(RB1_q_b[7]_PORT_B_address, RB1_q_b[7]_clock_1, , , );
RB1_q_b[7]_PORT_A_write_enable = GND;
RB1_q_b[7]_PORT_A_write_enable_reg = DFFE(RB1_q_b[7]_PORT_A_write_enable, RB1_q_b[7]_clock_0, , , );
RB1_q_b[7]_PORT_B_write_enable = SB1L2;
RB1_q_b[7]_PORT_B_write_enable_reg = DFFE(RB1_q_b[7]_PORT_B_write_enable, RB1_q_b[7]_clock_1, , , );
RB1_q_b[7]_clock_0 = clk;
RB1_q_b[7]_clock_1 = A1L5;
RB1_q_b[7]_PORT_B_data_out = MEMORY(RB1_q_b[7]_PORT_A_data_in_reg, RB1_q_b[7]_PORT_B_data_in_reg, RB1_q_b[7]_PORT_A_address_reg, RB1_q_b[7]_PORT_B_address_reg, RB1_q_b[7]_PORT_A_write_enable_reg, RB1_q_b[7]_PORT_B_write_enable_reg, , , RB1_q_b[7]_clock_0, RB1_q_b[7]_clock_1, , , , );
RB1_q_b[7] = RB1_q_b[7]_PORT_B_data_out[0];