phase_shift_sin.fit.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 51 行 · 第 1/5 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLRN_SIGNAL " "Info: Node sld_hub:sld_hub_inst\|CLRN_SIGNAL uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[3\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLRN_SIGNAL" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr1" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr0" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 380 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Node sld_signaltap:auto_signaltap_0\|reset_all uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\]" } } } } { "d:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1154 -1 0 } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear